From patchwork Thu Oct 8 13:31:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sjoerd Simons X-Patchwork-Id: 7352831 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C287FBEEA4 for ; Thu, 8 Oct 2015 13:34:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C55C520817 for ; Thu, 8 Oct 2015 13:34:54 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 79896207E1 for ; Thu, 8 Oct 2015 13:34:53 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 4ACA226683F; Thu, 8 Oct 2015 15:34:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 94801261ACD; Thu, 8 Oct 2015 15:31:53 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 9629F261ACD; Thu, 8 Oct 2015 15:31:51 +0200 (CEST) Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [93.93.135.160]) by alsa0.perex.cz (Postfix) with ESMTP id 7E844266698 for ; Thu, 8 Oct 2015 15:31:30 +0200 (CEST) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sjoerd) with ESMTPSA id 01D596092C1 Received: by dusk.luon.net (Postfix, from userid 1000) id BBBD924ED8; Thu, 8 Oct 2015 15:31:19 +0200 (CEST) From: Sjoerd Simons To: linux-rockchip@lists.infradead.org Date: Thu, 8 Oct 2015 15:31:16 +0200 Message-Id: <1444311079-2892-6-git-send-email-sjoerd.simons@collabora.co.uk> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1444311079-2892-1-git-send-email-sjoerd.simons@collabora.co.uk> References: <1444311079-2892-1-git-send-email-sjoerd.simons@collabora.co.uk> Cc: Mark Rutland , devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Russell King , Heiko Stuebner , Pawel Moll , Ian Campbell , Liam Girdwood , Michael Turquette , Takashi Iwai , Stephen Boyd , linux-kernel@vger.kernel.org, Rob Herring , Sjoerd Simons , Mark Brown , Kumar Gala , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v4 5/8] clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288 SoCs only feed those clocks, allow those clocks to change their parents all the way up the hierarchy. Signed-off-by: Sjoerd Simons Reviewed-by: Heiko Stuebner --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/clk/rockchip/clk-rk3288.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 90c1c9b..4e90252 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -317,25 +317,25 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(5), 15, 1, MFLAGS), - COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0, + COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(5), 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 4, GFLAGS), - COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0, + COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(9), 0, RK3288_CLKGATE_CON(4), 5, GFLAGS, - MUX(0, "spdif_mux", mux_spdif_p, 0, + MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(5), 8, 2, MFLAGS)), - GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", 0, + GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 6, GFLAGS), - COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0, + COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(40), 0, 7, DFLAGS, RK3288_CLKGATE_CON(4), 7, GFLAGS), - COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", 0, + COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(41), 0, RK3288_CLKGATE_CON(4), 8, GFLAGS, - MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, 0, + MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(40), 8, 2, MFLAGS)), - GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", 0, + GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT, RK3288_CLKGATE_CON(4), 9, GFLAGS), GATE(0, "sclk_acc_efuse", "xin24m", 0,