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[3/8] ASoC : dwc : add quirk for dwc controller instances

Message ID 1444320760-21936-4-git-send-email-alexander.deucher@amd.com (mailing list archive)
State New, archived
Headers show

Commit Message

Alex Deucher Oct. 8, 2015, 4:12 p.m. UTC
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>

Added a qurik to assign different base addresses for different
dwc controllers present on platform for playback and capture.

Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
---
 include/sound/designware_i2s.h |  3 +++
 sound/soc/dwc/designware_i2s.c | 26 +++++++++++++++++++++++---
 2 files changed, 26 insertions(+), 3 deletions(-)

Comments

Mark Brown Oct. 22, 2015, 3:05 p.m. UTC | #1
On Thu, Oct 08, 2015 at 12:12:36PM -0400, Alex Deucher wrote:
> From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
> 
> Added a qurik to assign different base addresses for different
> dwc controllers present on platform for playback and capture.

I don't understand what the above means, sorry.  Normally the address
ranges for devices are supplied via resources when the device is
registered.

> +	if (dev->quirks & DW_I2S_QUIRK_MULTI_DWC) {
> +		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> +			i2s_write_reg(dev->i2s_pbase, CER, 0);
> +			i2s_write_reg(dev->i2s_pbase, IER, 0);
> +		} else {
> +			i2s_write_reg(dev->i2s_cbase, CER, 0);
> +			i2s_write_reg(dev->i2s_cbase, IER, 0);
> +		}

This looks like it might be part of the previous change to merge
separate playback and capture instances of the controller into one
device rather than a separate change?  But perhaps what this is saying
is also that the controller instances aren't actually totally separate
after all and the prior change maps well onto the hardware...
diff mbox

Patch

diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h
index 8966ba7..48c8210 100644
--- a/include/sound/designware_i2s.h
+++ b/include/sound/designware_i2s.h
@@ -45,6 +45,9 @@  struct i2s_platform_data {
 	u32 snd_fmts;
 	u32 snd_rates;
 
+	#define DW_I2S_QUIRK_MULTI_DWC	(1 << 0)
+	unsigned int quirks;
+
 	void *play_dma_data;
 	void *capture_dma_data;
 	bool (*filter)(struct dma_chan *chan, void *slave);
diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c
index 374a83e..fd18a0e 100644
--- a/sound/soc/dwc/designware_i2s.c
+++ b/sound/soc/dwc/designware_i2s.c
@@ -94,6 +94,7 @@  struct dw_i2s_dev {
 	struct clk *clk;
 	int active;
 	unsigned int capability;
+	unsigned int quirks;
 	struct device *dev;
 
 	/* data related to DMA transfers b/w i2s and DMAC */
@@ -176,9 +177,20 @@  static void i2s_stop(struct dw_i2s_dev *dev,
 		}
 	}
 
-	if (!dev->active) {
-		i2s_write_reg(dev->i2s_pbase, CER, 0);
-		i2s_write_reg(dev->i2s_pbase, IER, 0);
+	if (dev->quirks & DW_I2S_QUIRK_MULTI_DWC) {
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			i2s_write_reg(dev->i2s_pbase, CER, 0);
+			i2s_write_reg(dev->i2s_pbase, IER, 0);
+		} else {
+			i2s_write_reg(dev->i2s_cbase, CER, 0);
+			i2s_write_reg(dev->i2s_cbase, IER, 0);
+		}
+
+	} else {
+		if (!dev->active) {
+			i2s_write_reg(dev->i2s_pbase, CER, 0);
+			i2s_write_reg(dev->i2s_pbase, IER, 0);
+		}
 	}
 }
 
@@ -599,6 +611,7 @@  static int dw_i2s_probe(struct platform_device *pdev)
 
 	if (pdata) {
 		dev->capability = pdata->cap;
+		dev->quirks = pdata->quirks;
 		clk_id = NULL;
 		ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
 	} else {
@@ -608,6 +621,13 @@  static int dw_i2s_probe(struct platform_device *pdev)
 	if (ret < 0)
 		return ret;
 
+	if (dev->quirks & DW_I2S_QUIRK_MULTI_DWC) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		dev->i2s_cbase = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(dev->i2s_cbase))
+			return PTR_ERR(dev->i2s_cbase);
+	}
+
 	if (dev->capability & DW_I2S_MASTER) {
 		if (pdata) {
 			dev->i2s_clk_cfg = pdata->i2s_clk_cfg;