From patchwork Sat Oct 10 16:05:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yakir Yang X-Patchwork-Id: 7367381 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EFA90BEEA4 for ; Sat, 10 Oct 2015 16:06:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D7964206FA for ; Sat, 10 Oct 2015 16:06:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2007B20830 for ; Sat, 10 Oct 2015 16:06:19 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zkwf4-0000pF-Q3; Sat, 10 Oct 2015 16:06:18 +0000 Received: from lucky1.263xmail.com ([211.157.147.132]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zkwet-0000gg-V7; Sat, 10 Oct 2015 16:06:09 +0000 Received: from ykk?rock-chips.com (unknown [192.168.167.226]) by lucky1.263xmail.com (Postfix) with SMTP id C8C6B5B6E7; Sun, 11 Oct 2015 00:05:43 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 867AB1B9583; Sun, 11 Oct 2015 00:05:40 +0800 (CST) X-RL-SENDER: ykk@rock-chips.com X-FST-TO: inki.dae@samsung.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: ykk@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 142044K4UM0; Sun, 11 Oct 2015 00:05:44 +0800 (CST) From: Yakir Yang To: Inki Dae , Andrzej Hajda , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Jingoo Han , Thierry Reding , Krzysztof Kozlowski , Rob Herring , joe@perches.com, Heiko Stuebner , Mark Yao Subject: [PATCH v6 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Date: Sun, 11 Oct 2015 00:05:39 +0800 Message-Id: <1444493139-28047-1-git-send-email-ykk@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444491357-26095-1-git-send-email-ykk@rock-chips.com> References: <1444491357-26095-1-git-send-email-ykk@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151010_090608_525723_945E1B02 X-CRM114-Status: GOOD ( 11.26 ) X-Spam-Score: 0.8 (/) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: djkurtz@chromium.org, dianders@chromium.org, Yakir Yang , Gustavo Padovan , linux-samsung-soc@vger.kernel.org, Russell King , linux-rockchip@lists.infradead.org, Kishon Vijay Abraham I , javier@osg.samsung.com, Kukjin Kim , robherring2@gmail.com, devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , Sean Paul , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Kumar Gala , ajaynumb@gmail.com, Andy Yan MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP RK3288 need some special registers setting, we can separate them out by the dev_type of plat_data. Signed-off-by: Yakir Yang --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: - Fix compile failed dut to phy_pd_addr variable misspell error drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++--------- drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++ 2 files changed, 60 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c index 861097a..21a3287 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -15,6 +15,8 @@ #include #include +#include + #include "analogix_dp_core.h" #include "analogix_dp_reg.h" @@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp) reg = SEL_24M | TX_DVDD_BIT_1_0625V; writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); + if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) { + writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1); + writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); + writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); + writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); + writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5); + } + reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); @@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, bool enable) { u32 reg; + u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; + + if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) + phy_pd_addr = ANALOGIX_DP_PD; switch (block) { case AUX_BLOCK: if (enable) { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg |= AUX_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg &= ~AUX_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } break; case CH0_BLOCK: if (enable) { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg |= CH0_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg &= ~CH0_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } break; case CH1_BLOCK: if (enable) { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg |= CH1_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg &= ~CH1_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } break; case CH2_BLOCK: if (enable) { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg |= CH2_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg &= ~CH2_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } break; case CH3_BLOCK: if (enable) { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg |= CH3_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg &= ~CH3_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } break; case ANALOG_TOTAL: if (enable) { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg |= DP_PHY_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } else { - reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD); + reg = readl(dp->reg_base + phy_pd_addr); reg &= ~DP_PHY_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } break; case POWER_ALL: if (enable) { reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | CH1_PD | CH0_PD; - writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(reg, dp->reg_base + phy_pd_addr); } else { - writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD); + writel(0x00, dp->reg_base + phy_pd_addr); } break; default: @@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp) analogix_dp_reset_aux(dp); /* Disable AUX transaction H/W retry */ - reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) | - AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; + if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) + reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | + AUX_HW_RETRY_COUNT_SEL(3) | + AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; + else + reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | + AUX_HW_RETRY_COUNT_SEL(0) | + AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h index 738db4c..337912b 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -22,6 +22,14 @@ #define ANALOGIX_DP_VIDEO_CTL_8 0x3C #define ANALOGIX_DP_VIDEO_CTL_10 0x44 +#define ANALOGIX_DP_PLL_REG_1 0xfc +#define ANALOGIX_DP_PLL_REG_2 0x9e4 +#define ANALOGIX_DP_PLL_REG_3 0x9e8 +#define ANALOGIX_DP_PLL_REG_4 0x9ec +#define ANALOGIX_DP_PLL_REG_5 0xa00 + +#define ANALOGIX_DP_PD 0x12c + #define ANALOGIX_DP_LANE_MAP 0x35C #define ANALOGIX_DP_ANALOG_CTL_1 0x370 @@ -154,6 +162,10 @@ #define VSYNC_POLARITY_CFG (0x1 << 1) #define HSYNC_POLARITY_CFG (0x1 << 0) +/* ANALOGIX_DP_PLL_REG_1 */ +#define REF_CLK_24M (0x1 << 1) +#define REF_CLK_27M (0x0 << 1) + /* ANALOGIX_DP_LANE_MAP */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)