[RFC,v4,07/11] drm/mediatek: enable hdmi output control bit

Commit Message

Philipp Zabel Oct. 16, 2015, 8:12 p.m. UTC

From: Jie Qiu <[e-mail]>

MT8173 HDMI hardware has a output control bit to enable/disable HDMI
output. Because of security reason, so this bit can ONLY be controlled
in ARM supervisor mode. Now the only way to enter ARM supervisor is the
ARM trusted firmware. So atf provides a API for HDMI driver to call to
setup this HDMI control bit to enable HDMI output in supervisor mode.

Signed-off-by: Jie Qiu <[e-mail]>
Signed-off-by: Philipp Zabel <[e-mail]>
---
 drivers/gpu/drm/mediatek/mtk_hdmi_hw.c   | 11 +++++++++++
 drivers/gpu/drm/mediatek/mtk_hdmi_regs.h |  1 +
 2 files changed, 12 insertions(+)

Patch

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
index 2e898fd..5093a7f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c
@@ -19,8 +19,15 @@ 
 #include <linux/delay.h>
 #include <linux/hdmi.h>
 #include <linux/io.h>
+#include <linux/psci.h>
 #include <linux/regmap.h>
 
+static int (*invoke_psci_fn)(u64, u64, u64, u64);
+typedef int (*psci_initcall_t)(const struct device_node *);
+
+asmlinkage int __invoke_psci_fn_hvc(u64, u64, u64, u64);
+asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64);
+
 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
 {
 	return readl(hdmi->regs + offset);
@@ -173,6 +180,10 @@  void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi,
 void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi,
 				   bool enable)
 {
+	invoke_psci_fn = __invoke_psci_fn_smc;
+	invoke_psci_fn(MTK_SIP_SET_AUTHORIZED_SECURE_REG,
+		       0x14000904, 0x80000000, 0);
+
 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
 			   HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
index b3d75e2..87cea50 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h
@@ -317,4 +317,5 @@ 
 #define RGS_HDMITX_5T1_EDG (0xf << 4)
 #define RGS_HDMITX_PLUG_TST BIT(0)
 
+#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001
 #endif