| Message ID | 1445343722-3312-2-git-send-email-jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Oct 20, 2015 at 03:22:01PM +0300, Jani Nikula wrote: > Prefer inclusive ranges for revision checks rather than "below B0". Per > specs A2 is not used, so revid <= A1 matches revid < B0. > > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_gem.c | 2 +- > drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- > drivers/gpu/drm/i915/intel_ddi.c | 2 +- > drivers/gpu/drm/i915/intel_dp.c | 2 +- > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > drivers/gpu/drm/i915/intel_lrc.c | 8 ++++---- > drivers/gpu/drm/i915/intel_pm.c | 6 +++--- > drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- > 9 files changed, 16 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index f222114981c0..28e71c32c0d5 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2501,6 +2501,7 @@ struct drm_i915_cmd_table { > #define SKL_REVID_F0 0x5 > > #define BXT_REVID_A0 0x0 > +#define BXT_REVID_A1 0x1 Except that I can't check this value here on the series: Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> > #define BXT_REVID_B0 0x3 > #define BXT_REVID_C0 0x9 > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index e57061ac0219..408ed6f8e33c 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -3826,7 +3826,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, > * cacheline, whereas normally such cachelines would get > * invalidated. > */ > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) > return -ENODEV; > > level = I915_CACHE_LLC; > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c > index 036b42bae827..863aa5c82466 100644 > --- a/drivers/gpu/drm/i915/i915_guc_submission.c > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c > @@ -161,7 +161,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, > data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; > /* WaRsDisableCoarsePowerGating:skl,bxt */ > if (!intel_enable_rc6(dev_priv->dev) || > - (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || > + (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || > (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) || > (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) > data[1] = 0; > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index b25e99a432fb..b80e0f5ec5dc 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -3247,7 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) > * On BXT A0/A1, sw needs to activate DDIA HPD logic and > * interrupts to check the external panel connection. > */ > - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) > + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1) > && port == PORT_B) > dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; > else > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 09bdd94ca3ba..92413e5d215c 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > break; > case PORT_B: > intel_encoder->hpd_pin = HPD_PORT_B; > - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) > + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) > intel_encoder->hpd_pin = HPD_PORT_A; > break; > case PORT_C: > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index 9eafa191cee2..35c6e211baf5 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -2039,7 +2039,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, > * On BXT A0/A1, sw needs to activate DDIA HPD logic and > * interrupts to check the external panel connection. > */ > - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) > + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) > intel_encoder->hpd_pin = HPD_PORT_A; > else > intel_encoder->hpd_pin = HPD_PORT_B; > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 88e12bdf79e2..0f5a1d63b51d 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1972,7 +1972,7 @@ static int logical_render_ring_init(struct drm_device *dev) > ring->init_hw = gen8_init_render_ring; > ring->init_context = gen8_init_rcs_context; > ring->cleanup = intel_fini_pipe_control; > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > ring->get_seqno = bxt_a_get_seqno; > ring->set_seqno = bxt_a_set_seqno; > } else { > @@ -2024,7 +2024,7 @@ static int logical_bsd_ring_init(struct drm_device *dev) > GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; > > ring->init_hw = gen8_init_common_ring; > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > ring->get_seqno = bxt_a_get_seqno; > ring->set_seqno = bxt_a_set_seqno; > } else { > @@ -2079,7 +2079,7 @@ static int logical_blt_ring_init(struct drm_device *dev) > GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; > > ring->init_hw = gen8_init_common_ring; > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > ring->get_seqno = bxt_a_get_seqno; > ring->set_seqno = bxt_a_set_seqno; > } else { > @@ -2109,7 +2109,7 @@ static int logical_vebox_ring_init(struct drm_device *dev) > GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; > > ring->init_hw = gen8_init_common_ring; > - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { > + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { > ring->get_seqno = bxt_a_get_seqno; > ring->set_seqno = bxt_a_set_seqno; > } else { > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index df22b9c75b2b..771eefb7c7ef 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4386,7 +4386,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) > struct drm_i915_private *dev_priv = dev->dev_private; > > /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ > - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) > + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) > return; > > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > @@ -4710,7 +4710,7 @@ static void gen9_enable_rps(struct drm_device *dev) > gen6_init_rps_frequencies(dev); > > /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ > - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { > + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) { > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > return; > } > @@ -4796,7 +4796,7 @@ static void gen9_enable_rc6(struct drm_device *dev) > * 3b: Enable Coarse Power Gating only when RC6 is enabled. > * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. > */ > - if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || > + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || > ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) > I915_WRITE(GEN9_PG_ENABLE, 0); > else > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index a49270525a38..d676512aa3c8 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -926,14 +926,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) > > if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || > INTEL_REVID(dev) == SKL_REVID_B0)) || > - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { > + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { > /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, > GEN9_DG_MIRROR_FIX_ENABLE); > } > > if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || > - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { > + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { > /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ > WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, > GEN9_RHWO_OPTIMIZATION_DISABLE); > @@ -962,7 +962,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) > > /* WaDisableMaskBasedCammingInRCC:skl,bxt */ > if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || > - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) > + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) > WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, > PIXEL_MASK_CAMMING_DISABLE); > > -- > 2.1.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, 21 Oct 2015, Daniel Vetter <daniel@ffwll.ch> wrote: > On Tue, Oct 20, 2015 at 03:22:01PM +0300, Jani Nikula wrote: >> Prefer inclusive ranges for revision checks rather than "below B0". Per >> specs A2 is not used, so revid <= A1 matches revid < B0. >> >> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.h | 1 + >> drivers/gpu/drm/i915/i915_gem.c | 2 +- >> drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- >> drivers/gpu/drm/i915/intel_ddi.c | 2 +- >> drivers/gpu/drm/i915/intel_dp.c | 2 +- >> drivers/gpu/drm/i915/intel_hdmi.c | 2 +- >> drivers/gpu/drm/i915/intel_lrc.c | 8 ++++---- >> drivers/gpu/drm/i915/intel_pm.c | 6 +++--- >> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- >> 9 files changed, 16 insertions(+), 15 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index f222114981c0..28e71c32c0d5 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -2501,6 +2501,7 @@ struct drm_i915_cmd_table { >> #define SKL_REVID_F0 0x5 >> >> #define BXT_REVID_A0 0x0 >> +#define BXT_REVID_A1 0x1 > > Except that I can't check this value here on the series: > > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Pushed them all. Thanks for the review and acks. BR, Jani. > >> #define BXT_REVID_B0 0x3 >> #define BXT_REVID_C0 0x9 >> >> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c >> index e57061ac0219..408ed6f8e33c 100644 >> --- a/drivers/gpu/drm/i915/i915_gem.c >> +++ b/drivers/gpu/drm/i915/i915_gem.c >> @@ -3826,7 +3826,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, >> * cacheline, whereas normally such cachelines would get >> * invalidated. >> */ >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) >> return -ENODEV; >> >> level = I915_CACHE_LLC; >> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c >> index 036b42bae827..863aa5c82466 100644 >> --- a/drivers/gpu/drm/i915/i915_guc_submission.c >> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c >> @@ -161,7 +161,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, >> data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; >> /* WaRsDisableCoarsePowerGating:skl,bxt */ >> if (!intel_enable_rc6(dev_priv->dev) || >> - (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || >> + (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || >> (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) || >> (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) >> data[1] = 0; >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> index b25e99a432fb..b80e0f5ec5dc 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -3247,7 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) >> * On BXT A0/A1, sw needs to activate DDIA HPD logic and >> * interrupts to check the external panel connection. >> */ >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1) >> && port == PORT_B) >> dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; >> else >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index 09bdd94ca3ba..92413e5d215c 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, >> break; >> case PORT_B: >> intel_encoder->hpd_pin = HPD_PORT_B; >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) >> intel_encoder->hpd_pin = HPD_PORT_A; >> break; >> case PORT_C: >> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c >> index 9eafa191cee2..35c6e211baf5 100644 >> --- a/drivers/gpu/drm/i915/intel_hdmi.c >> +++ b/drivers/gpu/drm/i915/intel_hdmi.c >> @@ -2039,7 +2039,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, >> * On BXT A0/A1, sw needs to activate DDIA HPD logic and >> * interrupts to check the external panel connection. >> */ >> - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) >> + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) >> intel_encoder->hpd_pin = HPD_PORT_A; >> else >> intel_encoder->hpd_pin = HPD_PORT_B; >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c >> index 88e12bdf79e2..0f5a1d63b51d 100644 >> --- a/drivers/gpu/drm/i915/intel_lrc.c >> +++ b/drivers/gpu/drm/i915/intel_lrc.c >> @@ -1972,7 +1972,7 @@ static int logical_render_ring_init(struct drm_device *dev) >> ring->init_hw = gen8_init_render_ring; >> ring->init_context = gen8_init_rcs_context; >> ring->cleanup = intel_fini_pipe_control; >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> ring->get_seqno = bxt_a_get_seqno; >> ring->set_seqno = bxt_a_set_seqno; >> } else { >> @@ -2024,7 +2024,7 @@ static int logical_bsd_ring_init(struct drm_device *dev) >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; >> >> ring->init_hw = gen8_init_common_ring; >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> ring->get_seqno = bxt_a_get_seqno; >> ring->set_seqno = bxt_a_set_seqno; >> } else { >> @@ -2079,7 +2079,7 @@ static int logical_blt_ring_init(struct drm_device *dev) >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; >> >> ring->init_hw = gen8_init_common_ring; >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> ring->get_seqno = bxt_a_get_seqno; >> ring->set_seqno = bxt_a_set_seqno; >> } else { >> @@ -2109,7 +2109,7 @@ static int logical_vebox_ring_init(struct drm_device *dev) >> GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; >> >> ring->init_hw = gen8_init_common_ring; >> - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { >> + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { >> ring->get_seqno = bxt_a_get_seqno; >> ring->set_seqno = bxt_a_set_seqno; >> } else { >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> index df22b9c75b2b..771eefb7c7ef 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -4386,7 +4386,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) >> struct drm_i915_private *dev_priv = dev->dev_private; >> >> /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ >> - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) >> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) >> return; >> >> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); >> @@ -4710,7 +4710,7 @@ static void gen9_enable_rps(struct drm_device *dev) >> gen6_init_rps_frequencies(dev); >> >> /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ >> - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { >> + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) { >> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); >> return; >> } >> @@ -4796,7 +4796,7 @@ static void gen9_enable_rc6(struct drm_device *dev) >> * 3b: Enable Coarse Power Gating only when RC6 is enabled. >> * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. >> */ >> - if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || >> + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || >> ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) >> I915_WRITE(GEN9_PG_ENABLE, 0); >> else >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c >> index a49270525a38..d676512aa3c8 100644 >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >> @@ -926,14 +926,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) >> >> if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || >> INTEL_REVID(dev) == SKL_REVID_B0)) || >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { >> /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ >> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, >> GEN9_DG_MIRROR_FIX_ENABLE); >> } >> >> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { >> /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ >> WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, >> GEN9_RHWO_OPTIMIZATION_DISABLE); >> @@ -962,7 +962,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) >> >> /* WaDisableMaskBasedCammingInRCC:skl,bxt */ >> if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || >> - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) >> + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) >> WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, >> PIXEL_MASK_CAMMING_DISABLE); >> >> -- >> 2.1.4 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f222114981c0..28e71c32c0d5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2501,6 +2501,7 @@ struct drm_i915_cmd_table { #define SKL_REVID_F0 0x5 #define BXT_REVID_A0 0x0 +#define BXT_REVID_A1 0x1 #define BXT_REVID_B0 0x3 #define BXT_REVID_C0 0x9 diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e57061ac0219..408ed6f8e33c 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3826,7 +3826,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, * cacheline, whereas normally such cachelines would get * invalidated. */ - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) return -ENODEV; level = I915_CACHE_LLC; diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 036b42bae827..863aa5c82466 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -161,7 +161,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; /* WaRsDisableCoarsePowerGating:skl,bxt */ if (!intel_enable_rc6(dev_priv->dev) || - (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || + (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || (IS_SKL_GT3(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0)) || (IS_SKL_GT4(dev) && (INTEL_REVID(dev) <= SKL_REVID_E0))) data[1] = 0; diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index b25e99a432fb..b80e0f5ec5dc 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -3247,7 +3247,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port) * On BXT A0/A1, sw needs to activate DDIA HPD logic and * interrupts to check the external panel connection. */ - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0) + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1) && port == PORT_B) dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; else diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 09bdd94ca3ba..92413e5d215c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -6087,7 +6087,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, break; case PORT_B: intel_encoder->hpd_pin = HPD_PORT_B; - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) intel_encoder->hpd_pin = HPD_PORT_A; break; case PORT_C: diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 9eafa191cee2..35c6e211baf5 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -2039,7 +2039,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, * On BXT A0/A1, sw needs to activate DDIA HPD logic and * interrupts to check the external panel connection. */ - if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0)) + if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) <= BXT_REVID_A1)) intel_encoder->hpd_pin = HPD_PORT_A; else intel_encoder->hpd_pin = HPD_PORT_B; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 88e12bdf79e2..0f5a1d63b51d 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1972,7 +1972,7 @@ static int logical_render_ring_init(struct drm_device *dev) ring->init_hw = gen8_init_render_ring; ring->init_context = gen8_init_rcs_context; ring->cleanup = intel_fini_pipe_control; - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { @@ -2024,7 +2024,7 @@ static int logical_bsd_ring_init(struct drm_device *dev) GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; ring->init_hw = gen8_init_common_ring; - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { @@ -2079,7 +2079,7 @@ static int logical_blt_ring_init(struct drm_device *dev) GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; ring->init_hw = gen8_init_common_ring; - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { @@ -2109,7 +2109,7 @@ static int logical_vebox_ring_init(struct drm_device *dev) GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; ring->init_hw = gen8_init_common_ring; - if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { + if (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1) { ring->get_seqno = bxt_a_get_seqno; ring->set_seqno = bxt_a_set_seqno; } else { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index df22b9c75b2b..771eefb7c7ef 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4386,7 +4386,7 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) struct drm_i915_private *dev_priv = dev->dev_private; /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) return; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -4710,7 +4710,7 @@ static void gen9_enable_rps(struct drm_device *dev) gen6_init_rps_frequencies(dev); /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ - if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { + if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) { intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); return; } @@ -4796,7 +4796,7 @@ static void gen9_enable_rc6(struct drm_device *dev) * 3b: Enable Coarse Power Gating only when RC6 is enabled. * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. */ - if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_A1)) || ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) I915_WRITE(GEN9_PG_ENABLE, 0); else diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a49270525a38..d676512aa3c8 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -926,14 +926,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 || INTEL_REVID(dev) == SKL_REVID_B0)) || - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, GEN9_DG_MIRROR_FIX_ENABLE); } if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) { + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) { /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, GEN9_RHWO_OPTIMIZATION_DISABLE); @@ -962,7 +962,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) /* WaDisableMaskBasedCammingInRCC:skl,bxt */ if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) || - (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) + (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A1)) WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, PIXEL_MASK_CAMMING_DISABLE);