From patchwork Tue Oct 20 16:04:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paauwe, Bob J" X-Patchwork-Id: 7448571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B8DDFBEEA4 for ; Tue, 20 Oct 2015 16:05:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ED575205B3 for ; Tue, 20 Oct 2015 16:05:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 161132054B for ; Tue, 20 Oct 2015 16:05:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D9EE6EC6E; Tue, 20 Oct 2015 09:05:45 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EF1D6EC6E for ; Tue, 20 Oct 2015 09:05:43 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 20 Oct 2015 09:05:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,707,1437462000"; d="scan'208";a="830985947" Received: from bpaauwe-desk.fm.intel.com ([10.1.134.218]) by orsmga002.jf.intel.com with ESMTP; 20 Oct 2015 09:05:17 -0700 From: Bob Paauwe To: intel-gfx Date: Tue, 20 Oct 2015 09:04:56 -0700 Message-Id: <1445357096-2653-1-git-send-email-bob.j.paauwe@intel.com> X-Mailer: git-send-email 2.4.3 Subject: [Intel-gfx] [PATCH] drm/i915/skl+: Enable gamma and CSC on bottom color. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To stay consisent with how we're programming all the other planes, enable gamma and CSC on the bottom color. Without this, we fail the the kms_universal_plane functional tests because the black primary plane is brighter (gamma corrected) than the disabled plane case. If the bottom color is also gamma/csc corrected, then the disiabled case will match the black plane case. testcase: igt/kms_universal_plane/universal-plane-pipe-[ABC]-functional CC: Konduru, Chandra cc: Kevin Strasser Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++++ drivers/gpu/drm/i915/intel_display.c | 7 +++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 724f057..9ad330b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4479,6 +4479,16 @@ enum skl_disp_power_wells { #define PIPEMISC_DITHER_TYPE_SP (0<<2) #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) +#define _PIPE_BOTTOM_COLOR_A 0x70034 +#define _PIPE_BOTTOM_COLOR_B 0x71034 +#define _PIPE_BOTTOM_COLOR_C 0x72034 +#define PIPE_BOTTOM_GAMMA_ENABLE (1<<31) +#define PIPE_BOTTOM_CSC_ENABLE (1<<30) +#define PIPE_BOTTOM_COLOR_MASK 0x3FFFFFFF +#define PIPE_BOTTOM_COLOR(pipe) _PIPE3(pipe, _PIPE_BOTTOM_COLOR_A, \ + _PIPE_BOTTOM_COLOR_B, \ + _PIPE_BOTTOM_COLOR_C) + #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) #define PIPEB_LINE_COMPARE_INT_EN (1<<29) #define PIPEB_HLINE_INT_EN (1<<28) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3b4bacf..7665730 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4949,6 +4949,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); + u32 bottom; if (WARN_ON(intel_crtc->active)) return; @@ -5033,6 +5034,12 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_wait_for_vblank(dev, hsw_workaround_pipe); intel_wait_for_vblank(dev, hsw_workaround_pipe); } + + if (INTEL_INFO(dev)->gen >= 9) { + bottom = I915_READ(PIPE_BOTTOM_COLOR(pipe)); + bottom |= (PIPE_BOTTOM_CSC_ENABLE | PIPE_BOTTOM_GAMMA_ENABLE); + I915_WRITE(PIPE_BOTTOM_COLOR(pipe), bottom); + } } static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)