From patchwork Tue Nov 10 09:27:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Michel_D=C3=A4nzer?= X-Patchwork-Id: 7589071 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D4E40C05C6 for ; Tue, 10 Nov 2015 09:28:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E402F20632 for ; Tue, 10 Nov 2015 09:28:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id F1DB320622 for ; Tue, 10 Nov 2015 09:28:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2CC866E7E2; Tue, 10 Nov 2015 01:28:01 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.gna.ch (darkcity.gna.ch [195.226.6.51]) by gabe.freedesktop.org (Postfix) with ESMTP id 0BED86E7E2 for ; Tue, 10 Nov 2015 01:28:00 -0800 (PST) Received: from kaveri (125-14-38-183.rev.home.ne.jp [125.14.38.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by darkcity.gna.ch (Postfix) with ESMTPSA id 792F0B2AD06 for ; Tue, 10 Nov 2015 10:27:58 +0100 (CET) Received: from daenzer by kaveri with local (Exim 4.86) (envelope-from ) id 1Zw5DX-0002L6-Fi for dri-devel@lists.freedesktop.org; Tue, 10 Nov 2015 18:27:55 +0900 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= To: dri-devel@lists.freedesktop.org Subject: [PATCH libdrm] radeon: Handle surface offsets exceeding 32 bits correctly Date: Tue, 10 Nov 2015 18:27:55 +0900 Message-Id: <1447147675-8953-1-git-send-email-michel@daenzer.net> X-Mailer: git-send-email 2.6.2 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Michel Dänzer The slice_size and bo_size fields were getting truncated to 32 bits. Signed-off-by: Michel Dänzer Reviewed-by: Alex Deucher --- radeon/radeon_surface.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index fad4bda..5ec9745 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -163,7 +163,7 @@ static void surf_minify(struct radeon_surface *surf, struct radeon_surface_level *surflevel, unsigned bpe, unsigned level, uint32_t xalign, uint32_t yalign, uint32_t zalign, - unsigned offset) + uint64_t offset) { surflevel->npix_x = mip_minify(surf->npix_x, level); surflevel->npix_y = mip_minify(surf->npix_y, level); @@ -184,7 +184,7 @@ static void surf_minify(struct radeon_surface *surf, surflevel->offset = offset; surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; - surflevel->slice_size = surflevel->pitch_bytes * surflevel->nblk_y; + surflevel->slice_size = (uint64_t)surflevel->pitch_bytes * surflevel->nblk_y; surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; } @@ -570,7 +570,7 @@ static void eg_surf_minify(struct radeon_surface *surf, unsigned mtilew, unsigned mtileh, unsigned mtileb, - unsigned offset) + uint64_t offset) { unsigned mtile_pr, mtile_ps; @@ -598,7 +598,7 @@ static void eg_surf_minify(struct radeon_surface *surf, surflevel->offset = offset; surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; - surflevel->slice_size = mtile_ps * mtileb * slice_pt; + surflevel->slice_size = (uint64_t)mtile_ps * mtileb * slice_pt; surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; } @@ -1415,7 +1415,7 @@ static void si_surf_minify(struct radeon_surface *surf, struct radeon_surface_level *surflevel, unsigned bpe, unsigned level, uint32_t xalign, uint32_t yalign, uint32_t zalign, - uint32_t slice_align, unsigned offset) + uint32_t slice_align, uint64_t offset) { if (level == 0) { surflevel->npix_x = surf->npix_x; @@ -1453,7 +1453,8 @@ static void si_surf_minify(struct radeon_surface *surf, surflevel->offset = offset; surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; - surflevel->slice_size = ALIGN(surflevel->pitch_bytes * surflevel->nblk_y, slice_align); + surflevel->slice_size = ALIGN((uint64_t)surflevel->pitch_bytes * surflevel->nblk_y, + (uint64_t)slice_align); surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; } @@ -1462,7 +1463,7 @@ static void si_surf_minify_2d(struct radeon_surface *surf, struct radeon_surface_level *surflevel, unsigned bpe, unsigned level, unsigned slice_pt, uint32_t xalign, uint32_t yalign, uint32_t zalign, - unsigned mtileb, unsigned offset) + unsigned mtileb, uint64_t offset) { unsigned mtile_pr, mtile_ps; @@ -1501,7 +1502,7 @@ static void si_surf_minify_2d(struct radeon_surface *surf, mtile_ps = (mtile_pr * surflevel->nblk_y) / yalign; surflevel->offset = offset; surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; - surflevel->slice_size = mtile_ps * mtileb * slice_pt; + surflevel->slice_size = (uint64_t)mtile_ps * mtileb * slice_pt; surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; }