From patchwork Mon Dec 7 06:40:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yakir Yang X-Patchwork-Id: 7780481 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 81C0ABEEE1 for ; Mon, 7 Dec 2015 06:41:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AB1DB20384 for ; Mon, 7 Dec 2015 06:41:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 707D620411 for ; Mon, 7 Dec 2015 06:41:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754449AbbLGGlI (ORCPT ); Mon, 7 Dec 2015 01:41:08 -0500 Received: from lucky1.263xmail.com ([211.157.147.131]:58835 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754655AbbLGGlH (ORCPT ); Mon, 7 Dec 2015 01:41:07 -0500 Received: from ykk?rock-chips.com (unknown [192.168.167.190]) by lucky1.263xmail.com (Postfix) with SMTP id 7E49B88596; Mon, 7 Dec 2015 14:40:42 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 30E072990B; Mon, 7 Dec 2015 14:40:37 +0800 (CST) X-RL-SENDER: ykk@rock-chips.com X-FST-TO: inki.dae@samsung.com X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: <606ed6f6156339eb619b729ad602fb80> X-ATTACHMENT-NUM: 0 X-SENDER: ykk@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [103.29.142.67]) by smtp.263.net (Postfix) whith ESMTP id 12403S0GAWL; Mon, 07 Dec 2015 14:40:40 +0800 (CST) From: Yakir Yang To: Inki Dae , Mark Yao , Jingoo Han , Heiko Stuebner Cc: Thierry Reding , Krzysztof Kozlowski , Rob Herring , Andrzej Hajda , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Russell King , emil.l.velikov@gmail.com, Gustavo Padovan , Kishon Vijay Abraham I , ajaynumb@gmail.com, javier@osg.samsung.com, Andy Yan , Yakir Yang , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v10 13/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Date: Mon, 7 Dec 2015 14:40:37 +0800 Message-Id: <1449470437-31476-1-git-send-email-ykk@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449470239-30667-1-git-send-email-ykk@rock-chips.com> References: <1449470239-30667-1-git-send-email-ykk@rock-chips.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are some IP limit on rk3288 that only support 4 physical lanes of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag. Signed-off-by: Yakir Yang Tested-by: Javier Martinez Canillas --- Changes in v10: - Remove the surplus "plat_data" check. (Heiko) - switch (dp->plat_data && dp->plat_data->dev_type) { + switch (dp->plat_data->dev_type) { Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: - Seprate the link-rate and lane-count limit out with the device_type flag. (Thierry) Changes in v3: None Changes in v2: None drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 33 ++++++++++++++-------- drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 4 +-- 2 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 5f542b7..a11504b 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) return; } - ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count, - dp->video_info.link_rate); + ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count, + dp->video_info.max_link_rate); if (ret) { dev_err(dp->dev, "unable to do link train\n"); return; @@ -1158,16 +1158,25 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp) struct device_node *dp_node = dp->dev->of_node; struct video_info *video_info = &dp->video_info; - if (of_property_read_u32(dp_node, "samsung,link-rate", - &video_info->link_rate)) { - dev_err(dp->dev, "failed to get link-rate\n"); - return -EINVAL; - } - - if (of_property_read_u32(dp_node, "samsung,lane-count", - &video_info->lane_count)) { - dev_err(dp->dev, "failed to get lane-count\n"); - return -EINVAL; + switch (dp->plat_data->dev_type) { + case RK3288_DP: + /* + * Like Rk3288 DisplayPort TRM indicate that "Main link + * containing 4 physical lanes of 2.7/1.62 Gbps/lane". + */ + video_info->max_link_rate = 0x0A; + video_info->max_lane_count = 0x04; + break; + case EXYNOS_DP: + /* + * NOTE: those property parseing code is used for + * providing backward compatibility for samsung platform. + */ + of_property_read_u32(dp_node, "samsung,link-rate", + &video_info->max_link_rate); + of_property_read_u32(dp_node, "samsung,lane-count", + &video_info->max_lane_count); + break; } return 0; diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h index e37cef6..e6f8243 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -129,8 +129,8 @@ struct video_info { enum color_coefficient ycbcr_coeff; enum color_depth color_depth; - enum link_rate_type link_rate; - enum link_lane_count_type lane_count; + enum link_rate_type max_link_rate; + enum link_lane_count_type max_lane_count; }; struct link_train {