[v2,13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12
diff mbox

Message ID 1449634091-1842-14-git-send-email-cw00.choi@samsung.com
State New, archived
Headers show

Commit Message

Chanwoo Choi Dec. 9, 2015, 4:08 a.m. UTC
This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data
between DRAM and DMC/ACP/C2C.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 arch/arm/boot/dts/exynos4x12.dtsi | 72 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

Comments

Krzysztof Kozlowski Dec. 10, 2015, 3:17 a.m. UTC | #1
On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.

s/noes/nodes/

> Exynos4x12 has the following AXI buses to translate data
> between DRAM and DMC/ACP/C2C.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
>  arch/arm/boot/dts/exynos4x12.dtsi | 72 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> index b77dac61ffb5..3bcf0939755e 100644
> --- a/arch/arm/boot/dts/exynos4x12.dtsi
> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> @@ -282,6 +282,78 @@
>  		clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
>  		#iommu-cells = <0>;
>  	};
> +
> +	bus_dmc: bus_dmc {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_DIV_DMC>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_dmc_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_acp: bus_acp {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_DIV_ACP>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_acp_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_c2c: bus_c2c {
> +		compatible = "samsung,exynos-bus";
> +		clocks = <&clock CLK_DIV_C2C>;
> +		clock-names = "bus";
> +		operating-points-v2 = <&bus_dmc_opp_table>;
> +		status = "disabled";
> +	};
> +
> +	bus_dmc_opp_table: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp00 {
> +			opp-hz = /bits/ 64 <100000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp01 {
> +			opp-hz = /bits/ 64 <134000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp02 {
> +			opp-hz = /bits/ 64 <160000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp03 {
> +			opp-hz = /bits/ 64 <200000000>;
> +			opp-microvolt = <950000>;

The exyno4_bus.c (from mainline) uses 267 MHz here. Why choosing 200 MHz?

Best regards,
Krzysztof

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Chanwoo Choi Dec. 10, 2015, 4:21 a.m. UTC | #2
On 2015? 12? 10? 12:17, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
> 
> s/noes/nodes/

OK.

> 
>> Exynos4x12 has the following AXI buses to translate data
>> between DRAM and DMC/ACP/C2C.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos4x12.dtsi | 72 +++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 72 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
>> index b77dac61ffb5..3bcf0939755e 100644
>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>> @@ -282,6 +282,78 @@
>>  		clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
>>  		#iommu-cells = <0>;
>>  	};
>> +
>> +	bus_dmc: bus_dmc {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_DIV_DMC>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_dmc_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_acp: bus_acp {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_DIV_ACP>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_acp_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_c2c: bus_c2c {
>> +		compatible = "samsung,exynos-bus";
>> +		clocks = <&clock CLK_DIV_C2C>;
>> +		clock-names = "bus";
>> +		operating-points-v2 = <&bus_dmc_opp_table>;
>> +		status = "disabled";
>> +	};
>> +
>> +	bus_dmc_opp_table: opp_table1 {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp00 {
>> +			opp-hz = /bits/ 64 <100000000>;
>> +			opp-microvolt = <900000>;
>> +		};
>> +		opp01 {
>> +			opp-hz = /bits/ 64 <134000000>;
>> +			opp-microvolt = <900000>;
>> +		};
>> +		opp02 {
>> +			opp-hz = /bits/ 64 <160000000>;
>> +			opp-microvolt = <900000>;
>> +		};
>> +		opp03 {
>> +			opp-hz = /bits/ 64 <200000000>;
>> +			opp-microvolt = <950000>;
> 
> The exyno4_bus.c (from mainline) uses 267 MHz here. Why choosing 200 MHz?

There is no special reason.
I'll change it (200MHz -> 267MHz).

Best Regards,
Chanwoo Choi

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Patch
diff mbox

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index b77dac61ffb5..3bcf0939755e 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -282,6 +282,78 @@ 
 		clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
 		#iommu-cells = <0>;
 	};
+
+	bus_dmc: bus_dmc {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_DMC>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_dmc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_acp: bus_acp {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_ACP>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_acp_opp_table>;
+		status = "disabled";
+	};
+
+	bus_c2c: bus_c2c {
+		compatible = "samsung,exynos-bus";
+		clocks = <&clock CLK_DIV_C2C>;
+		clock-names = "bus";
+		operating-points-v2 = <&bus_dmc_opp_table>;
+		status = "disabled";
+	};
+
+	bus_dmc_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <900000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <900000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <950000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1050000>;
+		};
+	};
+
+	bus_acp_opp_table: opp_table2 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <134000000>;
+			opp-microvolt = <900000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <160000000>;
+			opp-microvolt = <900000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <950000>;
+		};
+	};
 };
 
 &combiner {