| Message ID | 1449672244-5276-1-git-send-email-m.deepak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Dec 09, 2015 at 08:14:04PM +0530, Deepak M wrote: > Pipe is assigned based on the port, but it should be > based on current crtc. Correcting the same in this patch. > > v2: Use macro BXT_PIPE_SELECT(pipe) (Daniel) > > Signed-off-by: Deepak M <m.deepak@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 +--- > drivers/gpu/drm/i915/intel_dsi.c | 15 +++------------ > 2 files changed, 4 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index fa72be9..91dbb32 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8103,9 +8103,7 @@ enum skl_disp_power_wells { > #define RGB_FLIP_TO_BGR (1 << 2) > > #define BXT_PIPE_SELECT_MASK (7 << 7) > -#define BXT_PIPE_SELECT_C (2 << 7) > -#define BXT_PIPE_SELECT_B (1 << 7) > -#define BXT_PIPE_SELECT_A (0 << 7) > +#define BXT_PIPE_SELECT(pipe) ((pipe) << 7) > > /* BXT has dual link Z inversion overlap field */ > #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index f5df49b..12cfcf5 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -898,21 +898,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > I915_WRITE(MIPI_CTRL(port), tmp | > READ_REQUEST_PRIORITY_HIGH); > } else if (IS_BROXTON(dev)) { > - /* > - * FIXME: > - * BXT can connect any PIPE to any MIPI port. > - * Select the pipe based on the MIPI port read from > - * VBT for now. Pick PIPE A for MIPI port A and C > - * for port C. > - */ > + enum pipe pipe = intel_crtc->pipe; > + > tmp = I915_READ(MIPI_CTRL(port)); > tmp &= ~BXT_PIPE_SELECT_MASK; > > - if (port == PORT_A) > - tmp |= BXT_PIPE_SELECT_A; > - else if (port == PORT_C) > - tmp |= BXT_PIPE_SELECT_C; > - > + tmp |= BXT_PIPE_SELECT(pipe); > I915_WRITE(MIPI_CTRL(port), tmp); Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> There's way too much RMW going on in the DSI code though. Someone should probably do something about it. > } > > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Dec 09, 2015 at 03:54:33PM +0200, Ville Syrjälä wrote: > On Wed, Dec 09, 2015 at 08:14:04PM +0530, Deepak M wrote: > > Pipe is assigned based on the port, but it should be > > based on current crtc. Correcting the same in this patch. > > > > v2: Use macro BXT_PIPE_SELECT(pipe) (Daniel) > > > > Signed-off-by: Deepak M <m.deepak@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 4 +--- > > drivers/gpu/drm/i915/intel_dsi.c | 15 +++------------ > > 2 files changed, 4 insertions(+), 15 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index fa72be9..91dbb32 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -8103,9 +8103,7 @@ enum skl_disp_power_wells { > > #define RGB_FLIP_TO_BGR (1 << 2) > > > > #define BXT_PIPE_SELECT_MASK (7 << 7) > > -#define BXT_PIPE_SELECT_C (2 << 7) > > -#define BXT_PIPE_SELECT_B (1 << 7) > > -#define BXT_PIPE_SELECT_A (0 << 7) > > +#define BXT_PIPE_SELECT(pipe) ((pipe) << 7) > > > > /* BXT has dual link Z inversion overlap field */ > > #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > > index f5df49b..12cfcf5 100644 > > --- a/drivers/gpu/drm/i915/intel_dsi.c > > +++ b/drivers/gpu/drm/i915/intel_dsi.c > > @@ -898,21 +898,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) > > I915_WRITE(MIPI_CTRL(port), tmp | > > READ_REQUEST_PRIORITY_HIGH); > > } else if (IS_BROXTON(dev)) { > > - /* > > - * FIXME: > > - * BXT can connect any PIPE to any MIPI port. > > - * Select the pipe based on the MIPI port read from > > - * VBT for now. Pick PIPE A for MIPI port A and C > > - * for port C. > > - */ > > + enum pipe pipe = intel_crtc->pipe; > > + > > tmp = I915_READ(MIPI_CTRL(port)); > > tmp &= ~BXT_PIPE_SELECT_MASK; > > > > - if (port == PORT_A) > > - tmp |= BXT_PIPE_SELECT_A; > > - else if (port == PORT_C) > > - tmp |= BXT_PIPE_SELECT_C; > > - > > + tmp |= BXT_PIPE_SELECT(pipe); > > I915_WRITE(MIPI_CTRL(port), tmp); > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > There's way too much RMW going on in the DSI code though. Someone should > probably do something about it. Yeah that'd be nice. Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fa72be9..91dbb32 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8103,9 +8103,7 @@ enum skl_disp_power_wells { #define RGB_FLIP_TO_BGR (1 << 2) #define BXT_PIPE_SELECT_MASK (7 << 7) -#define BXT_PIPE_SELECT_C (2 << 7) -#define BXT_PIPE_SELECT_B (1 << 7) -#define BXT_PIPE_SELECT_A (0 << 7) +#define BXT_PIPE_SELECT(pipe) ((pipe) << 7) /* BXT has dual link Z inversion overlap field */ #define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index f5df49b..12cfcf5 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -898,21 +898,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder) I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); } else if (IS_BROXTON(dev)) { - /* - * FIXME: - * BXT can connect any PIPE to any MIPI port. - * Select the pipe based on the MIPI port read from - * VBT for now. Pick PIPE A for MIPI port A and C - * for port C. - */ + enum pipe pipe = intel_crtc->pipe; + tmp = I915_READ(MIPI_CTRL(port)); tmp &= ~BXT_PIPE_SELECT_MASK; - if (port == PORT_A) - tmp |= BXT_PIPE_SELECT_A; - else if (port == PORT_C) - tmp |= BXT_PIPE_SELECT_C; - + tmp |= BXT_PIPE_SELECT(pipe); I915_WRITE(MIPI_CTRL(port), tmp); }
Pipe is assigned based on the port, but it should be based on current crtc. Correcting the same in this patch. v2: Use macro BXT_PIPE_SELECT(pipe) (Daniel) Signed-off-by: Deepak M <m.deepak@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 +--- drivers/gpu/drm/i915/intel_dsi.c | 15 +++------------ 2 files changed, 4 insertions(+), 15 deletions(-)