From patchwork Wed Feb 10 23:51:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 78604 Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o1ANqe52024512 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 10 Feb 2010 23:53:19 GMT Received: from localhost ([127.0.0.1] helo=sfs-ml-4.v29.ch3.sourceforge.com) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NfMLC-0000rH-KG; Wed, 10 Feb 2010 23:51:30 +0000 Received: from sfi-mx-2.v28.ch3.sourceforge.com ([172.29.28.122] helo=mx.sourceforge.net) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1NfMLB-0000rA-64 for dri-devel@lists.sourceforge.net; Wed, 10 Feb 2010 23:51:29 +0000 Received-SPF: pass (sfi-mx-2.v28.ch3.sourceforge.com: domain of gmail.com designates 209.85.220.223 as permitted sender) client-ip=209.85.220.223; envelope-from=alexdeucher@gmail.com; helo=mail-fx0-f223.google.com; Received: from mail-fx0-f223.google.com ([209.85.220.223]) by sfi-mx-2.v28.ch3.sourceforge.com with esmtp (Exim 4.69) id 1NfMLA-0007Sp-1U for dri-devel@lists.sourceforge.net; Wed, 10 Feb 2010 23:51:29 +0000 Received: by fxm23 with SMTP id 23so620114fxm.2 for ; Wed, 10 Feb 2010 15:51:22 -0800 (PST) MIME-Version: 1.0 Received: by 10.223.77.91 with SMTP id f27mr1194777fak.60.1265845881294; Wed, 10 Feb 2010 15:51:21 -0800 (PST) Date: Wed, 10 Feb 2010 18:51:20 -0500 Message-ID: Subject: [PATCH] drm/radeon/kms: fix gart set/clear page on r6xx/r7xx From: Alex Deucher To: Dave Airlie , DRI Development Mailing List X-Spam-Score: -1.5 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record -0.0 DKIM_VERIFIED Domain Keys Identified Mail: signature passes verification 0.0 DKIM_SIGNED Domain Keys Identified Mail: message has a signature 0.0 AWL AWL: From: address is in the auto white-list X-Headers-End: 1NfMLA-0007Sp-1U X-BeenThere: dri-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.sourceforge.net X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 10 Feb 2010 23:53:23 +0000 (UTC) diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 1ecca29..213780b 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -353,6 +353,33 @@ void r600_hpd_fini(struct radeon_device *rdev) /* * R600 PCIE GART */ +#define R600_PTE_VALID (1 << 0) +#define R600_PTE_SYSTEM (1 << 1) +#define R600_PTE_SNOOPED (1 << 2) +#define R600_PTE_READABLE (1 << 5) +#define R600_PTE_WRITEABLE (1 << 6) + +int r600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) +{ + void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; + + if (i < 0 || i > rdev->gart.num_gpu_pages) + return -EINVAL; + + /* Flush VM TLBs, L2 */ + WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); + + addr = addr & 0xFFFFFFFFFFFFF000ULL; + addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; + addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; + writeq(addr, ((void __iomem *)ptr) + (i * 8)); + + /* flush hdp cache so updates hit vram */ + WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); + + return 0; +} + int r600_gart_clear_page(struct radeon_device *rdev, int i) { void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; @@ -360,8 +387,16 @@ int r600_gart_clear_page(struct radeon_device *rdev, int i) if (i < 0 || i > rdev->gart.num_gpu_pages) return -EINVAL; + + /* Flush VM TLBs, L2 */ + WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); + pte = 0; writeq(pte, ((void __iomem *)ptr) + (i * 8)); + + /* flush hdp cache so updates hit vram */ + WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); + return 0; } diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 9cb323a..30903f3 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1266,7 +1266,6 @@ extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); extern int r600_cp_resume(struct radeon_device *rdev); extern void r600_cp_fini(struct radeon_device *rdev); extern int r600_count_pipe_bits(uint32_t val); -extern int r600_gart_clear_page(struct radeon_device *rdev, int i); extern int r600_mc_wait_for_idle(struct radeon_device *rdev); extern int r600_pcie_gart_init(struct radeon_device *rdev); extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 6367946..8e1938a 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -506,6 +506,8 @@ int r600_wb_init(struct radeon_device *rdev); void r600_wb_fini(struct radeon_device *rdev); void r600_cp_commit(struct radeon_device *rdev); void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); +int r600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); +int r600_gart_clear_page(struct radeon_device *rdev, int i); uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); int r600_cs_parse(struct radeon_cs_parser *p); @@ -544,8 +546,8 @@ static struct radeon_asic r600_asic = { .vga_set_state = &r600_vga_set_state, .gpu_reset = &r600_gpu_reset, .gart_tlb_flush = &r600_pcie_gart_tlb_flush, - .gart_set_page = &rs600_gart_set_page, - .gart_clear_page = &rs600_gart_clear_page, + .gart_set_page = &r600_gart_set_page, + .gart_clear_page = &r600_gart_clear_page, .ring_test = &r600_ring_test, .ring_ib_execute = &r600_ring_ib_execute, .irq_set = &r600_irq_set, @@ -591,8 +593,8 @@ static struct radeon_asic rv770_asic = { .gpu_reset = &rv770_gpu_reset, .vga_set_state = &r600_vga_set_state, .gart_tlb_flush = &r600_pcie_gart_tlb_flush, - .gart_set_page = &rs600_gart_set_page, - .gart_clear_page = &rs600_gart_clear_page, + .gart_set_page = &r600_gart_set_page, + .gart_clear_page = &r600_gart_clear_page, .ring_test = &r600_ring_test, .ring_ib_execute = &r600_ring_ib_execute, .irq_set = &r600_irq_set,