From patchwork Tue Jan 5 12:52:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 7954711 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 58CD49F716 for ; Tue, 5 Jan 2016 12:53:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 449BF203B5 for ; Tue, 5 Jan 2016 12:53:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D7F0820382 for ; Tue, 5 Jan 2016 12:53:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751472AbcAEMxL (ORCPT ); Tue, 5 Jan 2016 07:53:11 -0500 Received: from mailout1.w1.samsung.com ([210.118.77.11]:45707 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751608AbcAEMxJ (ORCPT ); Tue, 5 Jan 2016 07:53:09 -0500 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O0H00MXFD4IQO40@mailout1.w1.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 05 Jan 2016 12:53:07 +0000 (GMT) X-AuditID: cbfec7f4-f79026d00000418a-0d-568bbcb23883 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 02.FC.16778.2BCBB865; Tue, 5 Jan 2016 12:53:06 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O0H00EDGD48I840@eusync2.samsung.com>; Tue, 05 Jan 2016 12:53:06 +0000 (GMT) From: Marek Szyprowski To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Inki Dae , Daniel Vetter , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , Joonyoung Shim , Seung-Woo Kim , Andrzej Hajda , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Tobias Jakobi , Gustavo Padovan Subject: [PATCH 3/4] drm/exynos: mixer: properly update all planes on the same vblank event Date: Tue, 05 Jan 2016 13:52:52 +0100 Message-id: <1451998373-13708-4-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <1451998373-13708-1-git-send-email-m.szyprowski@samsung.com> References: <1451998373-13708-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBLMWRmVeSWpSXmKPExsVy+t/xK7qb9nSHGWzcYmZxa905VouNM9az WvzfNpHZ4srX92wWOx/sYreYdH8Ci8WLexdZLF6/MLSYcX4fk8XaI3fZLWZMfslm0bb6A6vF 938LmRx4PfZ+W8DiMe9koMf97uNMHv+OsXvsnLSXyaNvyypGj8+b5ALYo7hsUlJzMstSi/Tt Ergydp98zl7wRqHizovXTA2M96S7GDk5JARMJNpbZ7BB2GISF+6tB7K5OIQEljJKvPm7EMpp YpJ4/fArWBWbgKFE19suMFtEwE2i6fBMVpAiZoFfzBKtd/axgySEBWIlVq48wtTFyMHBIqAq sXllLEiYV8BDYsb1yawQ2+Qk/r9cwQRicwp4Spz+NJkRpFwIqObLlaAJjLwLGBlWMYqmliYX FCel5xrqFSfmFpfmpesl5+duYoSE55cdjIuPWR1iFOBgVOLh5XjZFSbEmlhWXJl7iFGCg1lJ hNd5SXeYEG9KYmVValF+fFFpTmrxIUZpDhYlcd65u96HCAmkJ5akZqemFqQWwWSZODilGhjl Z5o8cu3h+/NfUKdVuGO28d6iKmEJMe3WZZ8LKx/9fLJCfK60aWJthVTbXP4rew+v5ivcErR0 +nfWsxO1V+484/DahvepwqSg1g3+x/raS5X2TTi0W+626WsR/8bLFiv3By9f8q07WIFtGpeQ k1zN0RADbtZVk1/oPVY1vr1CMurI4umJupeUWIozEg21mIuKEwG08vnuSwIAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch also moves mixer_vsync_set_update() to newly introduced mixer_atomic_begin/flush callbacks. This ensures that all mixer planes will be updated on the same vsync event. Signed-off-by: Marek Szyprowski --- drivers/gpu/drm/exynos/exynos_mixer.c | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index bf148dc3623c..b5fbc1cbf024 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -516,7 +516,6 @@ static void vp_video_buffer(struct mixer_context *ctx, } spin_lock_irqsave(&res->reg_slock, flags); - mixer_vsync_set_update(ctx, false); /* interlace or progressive scan mode */ val = (ctx->interlace ? ~0 : 0); @@ -567,7 +566,6 @@ static void vp_video_buffer(struct mixer_context *ctx, mixer_cfg_vp_blend(ctx); mixer_run(ctx); - mixer_vsync_set_update(ctx, true); spin_unlock_irqrestore(&res->reg_slock, flags); mixer_regs_dump(ctx); @@ -642,7 +640,6 @@ static void mixer_graph_buffer(struct mixer_context *ctx, ctx->interlace = false; spin_lock_irqsave(&res->reg_slock, flags); - mixer_vsync_set_update(ctx, false); /* setup format */ mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), @@ -691,7 +688,6 @@ static void mixer_graph_buffer(struct mixer_context *ctx, mixer_run(ctx); - mixer_vsync_set_update(ctx, true); spin_unlock_irqrestore(&res->reg_slock, flags); mixer_regs_dump(ctx); @@ -718,7 +714,6 @@ static void mixer_win_reset(struct mixer_context *ctx) unsigned long flags; spin_lock_irqsave(&res->reg_slock, flags); - mixer_vsync_set_update(ctx, false); mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK); @@ -749,7 +744,6 @@ static void mixer_win_reset(struct mixer_context *ctx) if (ctx->vp_enabled) mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE); - mixer_vsync_set_update(ctx, true); spin_unlock_irqrestore(&res->reg_slock, flags); } @@ -980,6 +974,16 @@ static void mixer_disable_vblank(struct exynos_drm_crtc *crtc) mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); } +static void mixer_atomic_begin(struct exynos_drm_crtc *crtc) +{ + struct mixer_context *mixer_ctx = crtc->ctx; + + if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) + return; + + mixer_vsync_set_update(mixer_ctx, false); +} + static void mixer_update_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane) { @@ -1009,12 +1013,18 @@ static void mixer_disable_plane(struct exynos_drm_crtc *crtc, return; spin_lock_irqsave(&res->reg_slock, flags); - mixer_vsync_set_update(mixer_ctx, false); - mixer_cfg_layer(mixer_ctx, plane->index, 0, false); + spin_unlock_irqrestore(&res->reg_slock, flags); +} + +static void mixer_atomic_flush(struct exynos_drm_crtc *crtc) +{ + struct mixer_context *mixer_ctx = crtc->ctx; + + if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) + return; mixer_vsync_set_update(mixer_ctx, true); - spin_unlock_irqrestore(&res->reg_slock, flags); } static void mixer_wait_for_vblank(struct exynos_drm_crtc *crtc) @@ -1055,6 +1065,8 @@ static void mixer_enable(struct exynos_drm_crtc *crtc) pm_runtime_get_sync(ctx->dev); + mixer_vsync_set_update(ctx, false); + mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) { @@ -1063,6 +1075,8 @@ static void mixer_enable(struct exynos_drm_crtc *crtc) } mixer_win_reset(ctx); + mixer_vsync_set_update(ctx, true); + set_bit(MXR_BIT_POWERED, &ctx->flags); } @@ -1113,8 +1127,10 @@ static const struct exynos_drm_crtc_ops mixer_crtc_ops = { .enable_vblank = mixer_enable_vblank, .disable_vblank = mixer_disable_vblank, .wait_for_vblank = mixer_wait_for_vblank, + .atomic_begin = mixer_atomic_begin, .update_plane = mixer_update_plane, .disable_plane = mixer_disable_plane, + .atomic_flush = mixer_atomic_flush, .atomic_check = mixer_atomic_check, };