[11/13] drm/i915: Cache ringbuffer GTT address
diff mbox

Message ID 1452252592-24803-12-git-send-email-tvrtko.ursulin@linux.intel.com
State New
Headers show

Commit Message

Tvrtko Ursulin Jan. 8, 2016, 11:29 a.m. UTC
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Purpose is to avoid calling i915_gem_obj_ggtt_offset from the
interrupt context without the big lock held.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c        | 3 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
 3 files changed, 5 insertions(+), 2 deletions(-)

Comments

Chris Wilson Jan. 8, 2016, 11:37 a.m. UTC | #1
On Fri, Jan 08, 2016 at 11:29:50AM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Purpose is to avoid calling i915_gem_obj_ggtt_offset from the
> interrupt context without the big lock held.

No. Move to tracking VMA.
-Chris
Daniel Vetter Jan. 11, 2016, 8:49 a.m. UTC | #2
On Fri, Jan 08, 2016 at 11:29:50AM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Purpose is to avoid calling i915_gem_obj_ggtt_offset from the
> interrupt context without the big lock held.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c        | 3 +--
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
>  3 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 5b3795815d8e..70c511ef6b12 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -345,7 +345,6 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
>  	struct intel_engine_cs *ring = rq->ring;
>  	struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
>  	struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
> -	struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
>  	struct page *page;
>  	uint32_t *reg_state;
>  
> @@ -355,7 +354,7 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
>  	reg_state = kmap_atomic(page);
>  
>  	reg_state[CTX_RING_TAIL+1] = rq->tail;
> -	reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
> +	reg_state[CTX_RING_BUFFER_START+1] = rq->ringbuf->gtt_start;
>  
>  	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
>  		/* True 32b PPGTT with dynamic page allocation: update PDP
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 339701d7a9a5..9094ce254125 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1988,6 +1988,7 @@ void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
>  	else
>  		iounmap(ringbuf->virtual_start);
>  	ringbuf->virtual_start = NULL;
> +	ringbuf->gtt_start = 0;
>  	i915_gem_object_ggtt_unpin(ringbuf->obj);
>  }
>  
> @@ -2054,6 +2055,8 @@ int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
>  		}
>  	}
>  
> +	ringbuf->gtt_start = i915_gem_obj_ggtt_offset(obj);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 0b91a4b77359..25d3716228ae 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -98,6 +98,7 @@ struct intel_ring_hangcheck {
>  struct intel_ringbuffer {
>  	struct drm_i915_gem_object *obj;
>  	void __iomem *virtual_start;
> +	u64 gtt_start;

gtt_offset, because consistency. Or vma, as Chris suggested.
-Daniel

>  
>  	struct intel_engine_cs *ring;
>  	struct list_head link;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Dave Gordon Jan. 11, 2016, 4:16 p.m. UTC | #3
On 08/01/16 11:29, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Purpose is to avoid calling i915_gem_obj_ggtt_offset from the
> interrupt context without the big lock held.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_lrc.c        | 3 +--
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>   drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
>   3 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 5b3795815d8e..70c511ef6b12 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -345,7 +345,6 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
>   	struct intel_engine_cs *ring = rq->ring;
>   	struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
>   	struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
> -	struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
>   	struct page *page;
>   	uint32_t *reg_state;
>
> @@ -355,7 +354,7 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
>   	reg_state = kmap_atomic(page);
>
>   	reg_state[CTX_RING_TAIL+1] = rq->tail;
> -	reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
> +	reg_state[CTX_RING_BUFFER_START+1] = rq->ringbuf->gtt_start;
>
>   	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
>   		/* True 32b PPGTT with dynamic page allocation: update PDP
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 339701d7a9a5..9094ce254125 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1988,6 +1988,7 @@ void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
>   	else
>   		iounmap(ringbuf->virtual_start);
>   	ringbuf->virtual_start = NULL;
> +	ringbuf->gtt_start = 0;

Zero isn't an invalid GTT address (although it does cause confusion).
Maybe we should define a suitable value to indicate not-an-address?
Anything with low bits set, or above 4Gb, is not valid, so perhaps:

#define	I915_GTT_BAD_ADDRESS		(~(u64)0)

.Dave.

>   	i915_gem_object_ggtt_unpin(ringbuf->obj);
>   }
>
> @@ -2054,6 +2055,8 @@ int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
>   		}
>   	}
>
> +	ringbuf->gtt_start = i915_gem_obj_ggtt_offset(obj);
> +
>   	return 0;
>   }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 0b91a4b77359..25d3716228ae 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -98,6 +98,7 @@ struct intel_ring_hangcheck {
>   struct intel_ringbuffer {
>   	struct drm_i915_gem_object *obj;
>   	void __iomem *virtual_start;
> +	u64 gtt_start;
>
>   	struct intel_engine_cs *ring;
>   	struct list_head link;
>
Tvrtko Ursulin Jan. 11, 2016, 5:44 p.m. UTC | #4
On 11/01/16 16:16, Dave Gordon wrote:
> On 08/01/16 11:29, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Purpose is to avoid calling i915_gem_obj_ggtt_offset from the
>> interrupt context without the big lock held.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_lrc.c        | 3 +--
>>   drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>>   drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
>>   3 files changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
>> b/drivers/gpu/drm/i915/intel_lrc.c
>> index 5b3795815d8e..70c511ef6b12 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -345,7 +345,6 @@ static int execlists_update_context(struct
>> drm_i915_gem_request *rq)
>>       struct intel_engine_cs *ring = rq->ring;
>>       struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
>>       struct drm_i915_gem_object *ctx_obj =
>> rq->ctx->engine[ring->id].state;
>> -    struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
>>       struct page *page;
>>       uint32_t *reg_state;
>>
>> @@ -355,7 +354,7 @@ static int execlists_update_context(struct
>> drm_i915_gem_request *rq)
>>       reg_state = kmap_atomic(page);
>>
>>       reg_state[CTX_RING_TAIL+1] = rq->tail;
>> -    reg_state[CTX_RING_BUFFER_START+1] =
>> i915_gem_obj_ggtt_offset(rb_obj);
>> +    reg_state[CTX_RING_BUFFER_START+1] = rq->ringbuf->gtt_start;
>>
>>       if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
>>           /* True 32b PPGTT with dynamic page allocation: update PDP
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 339701d7a9a5..9094ce254125 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -1988,6 +1988,7 @@ void intel_unpin_ringbuffer_obj(struct
>> intel_ringbuffer *ringbuf)
>>       else
>>           iounmap(ringbuf->virtual_start);
>>       ringbuf->virtual_start = NULL;
>> +    ringbuf->gtt_start = 0;
>
> Zero isn't an invalid GTT address (although it does cause confusion).
> Maybe we should define a suitable value to indicate not-an-address?
> Anything with low bits set, or above 4Gb, is not valid, so perhaps:

Oh yes, it crossed my mind and then I forgot about it, so thanks!

> #define    I915_GTT_BAD_ADDRESS        (~(u64)0)

It would match current behaviour of i915_gem_obj_offset(_view) of 
returning -1 when VMA is not found so I think it is good enough to go 
with this approach.

Regards,

Tvrtko

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5b3795815d8e..70c511ef6b12 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -345,7 +345,6 @@  static int execlists_update_context(struct drm_i915_gem_request *rq)
 	struct intel_engine_cs *ring = rq->ring;
 	struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
 	struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
-	struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
 	struct page *page;
 	uint32_t *reg_state;
 
@@ -355,7 +354,7 @@  static int execlists_update_context(struct drm_i915_gem_request *rq)
 	reg_state = kmap_atomic(page);
 
 	reg_state[CTX_RING_TAIL+1] = rq->tail;
-	reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
+	reg_state[CTX_RING_BUFFER_START+1] = rq->ringbuf->gtt_start;
 
 	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
 		/* True 32b PPGTT with dynamic page allocation: update PDP
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 339701d7a9a5..9094ce254125 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1988,6 +1988,7 @@  void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
 	else
 		iounmap(ringbuf->virtual_start);
 	ringbuf->virtual_start = NULL;
+	ringbuf->gtt_start = 0;
 	i915_gem_object_ggtt_unpin(ringbuf->obj);
 }
 
@@ -2054,6 +2055,8 @@  int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
 		}
 	}
 
+	ringbuf->gtt_start = i915_gem_obj_ggtt_offset(obj);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 0b91a4b77359..25d3716228ae 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -98,6 +98,7 @@  struct intel_ring_hangcheck {
 struct intel_ringbuffer {
 	struct drm_i915_gem_object *obj;
 	void __iomem *virtual_start;
+	u64 gtt_start;
 
 	struct intel_engine_cs *ring;
 	struct list_head link;