From patchwork Sun Jan 10 15:41:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 7997151 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E7F439F1CC for ; Sun, 10 Jan 2016 15:43:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 278D52024C for ; Sun, 10 Jan 2016 15:43:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 46965201F4 for ; Sun, 10 Jan 2016 15:43:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757243AbcAJPm6 (ORCPT ); Sun, 10 Jan 2016 10:42:58 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:58946 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756609AbcAJPmN (ORCPT ); Sun, 10 Jan 2016 10:42:13 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u0AFfcIU031753; Sun, 10 Jan 2016 09:41:38 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u0AFfcDl004272; Sun, 10 Jan 2016 09:41:38 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Sun, 10 Jan 2016 09:41:37 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u0AFfUKj027623; Sun, 10 Jan 2016 09:41:35 -0600 From: Kishon Vijay Abraham I To: Tony Lindgren , Bjorn Helgaas , CC: Russell King , Suman Anna , , , , , Subject: [PATCH 1/3] ARM: DRA7: hwmod: Add reset data for PCIe Date: Sun, 10 Jan 2016 21:11:26 +0530 Message-ID: <1452440488-28398-2-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1452440488-28398-1-git-send-email-kishon@ti.com> References: <1452440488-28398-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add PCIe reset data to PCIe hwmods on DRA7x. Reviewed-by: Suman Anna Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 15 +++++++++++++++ arch/arm/mach-omap2/prm7xx.h | 1 + 2 files changed, 16 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index ee4e044..1281deb 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1532,14 +1532,21 @@ static struct omap_hwmod_class dra7xx_pciess_hwmod_class = { }; /* pcie1 */ +static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = { + { .name = "pcie", .rst_shift = 0 }, +}; + static struct omap_hwmod dra7xx_pciess1_hwmod = { .name = "pcie1", .class = &dra7xx_pciess_hwmod_class, .clkdm_name = "pcie_clkdm", + .rst_lines = dra7xx_pciess1_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets), .main_clk = "l4_root_clk_div", .prcm = { .omap4 = { .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, @@ -1547,14 +1554,22 @@ static struct omap_hwmod dra7xx_pciess1_hwmod = { }; /* pcie2 */ +static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = { + { .name = "pcie", .rst_shift = 1 }, +}; + +/* pcie2 */ static struct omap_hwmod dra7xx_pciess2_hwmod = { .name = "pcie2", .class = &dra7xx_pciess_hwmod_class, .clkdm_name = "pcie_clkdm", + .rst_lines = dra7xx_pciess2_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets), .main_clk = "l4_root_clk_div", .prcm = { .omap4 = { .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h index cc1e6a2..294deed 100644 --- a/arch/arm/mach-omap2/prm7xx.h +++ b/arch/arm/mach-omap2/prm7xx.h @@ -360,6 +360,7 @@ /* PRM.L3INIT_PRM register offsets */ #define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 #define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010 #define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 #define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c #define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030