From patchwork Mon Jan 11 10:45:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8001431 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 62BFCBEEE5 for ; Mon, 11 Jan 2016 10:47:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0AEC520295 for ; Mon, 11 Jan 2016 10:47:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7DCBA2028D for ; Mon, 11 Jan 2016 10:47:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3BC816E2E6; Mon, 11 Jan 2016 02:47:51 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by gabe.freedesktop.org (Postfix) with ESMTPS id DF2906E2E1 for ; Mon, 11 Jan 2016 02:47:11 -0800 (PST) Received: by mail-wm0-f66.google.com with SMTP id b14so25704602wmb.1 for ; Mon, 11 Jan 2016 02:47:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ye6iWjscDDiGuKPPeDjEl2ON+uhOSqO+TtVwfCR5ktE=; b=tfghVsjRbZ+Vf/KMneo3r3Cbb/PNJY86AcpDaw7NKFUCh1jHyJp894piCBG6tLSnaW 3MIHz0cWyB2Fdd+jGXifpLOj5TcJnZZR9971+t4VLX+KaNEI5500EdIOT1GEmP23rL26 39Dx4Fhlu4C5J/IAOQI5h0ELtbPP8xKEDFh05ti6Eh5I3qDjrXo29ZMkxP3GWflVCmsw 7n0hhPWuwmsuBCkJl1nUn7aV5xjDZ4JaEY1bqToEFt545ii8yGOuHBuJbqNmnIbc7aE7 1iktHoX8Qo8qewjfq/0BGVYbUU41wdAtH9jyKX4H0Rv7p6B28Uqq4yr011kiRFhZztvh 62Cg== X-Received: by 10.28.57.214 with SMTP id g205mr2842002wma.20.1452509229990; Mon, 11 Jan 2016 02:47:09 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id t3sm118879383wjz.11.2016.01.11.02.47.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 11 Jan 2016 02:47:08 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 11 Jan 2016 10:45:08 +0000 Message-Id: <1452509174-16671-38-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.7.0.rc3 In-Reply-To: <1452509174-16671-1-git-send-email-chris@chris-wilson.co.uk> References: <1452503961-14837-1-git-send-email-chris@chris-wilson.co.uk> <1452509174-16671-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 124/190] drm/i915: Track pinned vma inside guc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since the guc allocates and pins and object into the GGTT for its usage, it is more natural to use that pinned VMA as our resource cookie. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 10 +- drivers/gpu/drm/i915/i915_guc_submission.c | 142 ++++++++++++++--------------- drivers/gpu/drm/i915/intel_guc.h | 9 +- drivers/gpu/drm/i915/intel_guc_loader.c | 7 +- 4 files changed, 78 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 6b14c59828e3..d186d256f467 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2512,15 +2512,15 @@ static int i915_guc_log_dump(struct seq_file *m, void *data) struct drm_info_node *node = m->private; struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj; - u32 *log; + struct drm_i915_gem_object *obj; int i = 0, pg; - if (!log_obj) + if (dev_priv->guc.log == NULL) return 0; - for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) { - log = kmap_atomic(i915_gem_object_get_page(log_obj, pg)); + obj = dev_priv->guc.log->obj; + for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { + u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index c4d8c34092a9..baa5c34757ba 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -181,7 +181,7 @@ static void guc_init_doorbell(struct intel_guc *guc, struct guc_doorbell_info *doorbell; void *base; - base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); + base = kmap_atomic(i915_gem_object_get_page(client->client->obj, 0)); doorbell = base + client->doorbell_offset; doorbell->db_status = 1; @@ -198,7 +198,7 @@ static int guc_ring_doorbell(struct i915_guc_client *gc) void *base; int attempt = 2, ret = -EAGAIN; - base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); + base = kmap_atomic(i915_gem_object_get_page(gc->client->obj, 0)); desc = base + gc->proc_desc_offset; /* Update the tail so it is visible to GuC */ @@ -260,7 +260,7 @@ static void guc_disable_doorbell(struct intel_guc *guc, i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id); int value; - base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); + base = kmap_atomic(i915_gem_object_get_page(client->client->obj, 0)); doorbell = base + client->doorbell_offset; doorbell->db_status = 0; @@ -343,7 +343,7 @@ static void guc_init_proc_desc(struct intel_guc *guc, struct guc_process_desc *desc; void *base; - base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); + base = kmap_atomic(i915_gem_object_get_page(client->client->obj, 0)); desc = base + client->proc_desc_offset; memset(desc, 0, sizeof(*desc)); @@ -432,17 +432,15 @@ static void guc_init_ctx_desc(struct intel_guc *guc, * XXX: May make debug easier to have it mapped */ desc.db_trigger_cpu = 0; - desc.db_trigger_uk = client->doorbell_offset + - i915_gem_obj_ggtt_offset(client->client_obj); + desc.db_trigger_uk = + client->doorbell_offset + client->client->node.start; desc.db_trigger_phy = client->doorbell_offset + - sg_dma_address(client->client_obj->pages->sgl); + sg_dma_address(client->client->obj->pages->sgl); - desc.process_desc = client->proc_desc_offset + - i915_gem_obj_ggtt_offset(client->client_obj); - - desc.wq_addr = client->wq_offset + - i915_gem_obj_ggtt_offset(client->client_obj); + desc.process_desc = + client->proc_desc_offset + client->client->node.start; + desc.wq_addr = client->wq_offset + client->client->node.start; desc.wq_size = client->wq_size; /* @@ -452,7 +450,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc, desc.desc_private = (uintptr_t)client; /* Pool context is pinned already */ - sg = guc->ctx_pool_obj->pages; + sg = guc->ctx_pool->obj->pages; sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), sizeof(desc) * client->ctx_index); } @@ -465,7 +463,7 @@ static void guc_fini_ctx_desc(struct intel_guc *guc, memset(&desc, 0, sizeof(desc)); - sg = guc->ctx_pool_obj->pages; + sg = guc->ctx_pool->obj->pages; sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), sizeof(desc) * client->ctx_index); } @@ -485,7 +483,7 @@ int i915_guc_wq_check_space(struct i915_guc_client *gc) if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) return 0; - base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); + base = kmap_atomic(i915_gem_object_get_page(gc->client->obj, 0)); desc = base + gc->proc_desc_offset; while (timeout_counter-- > 0) { @@ -533,7 +531,7 @@ static int guc_add_workqueue_item(struct i915_guc_client *gc, WARN_ON(wq_off & 3); /* wq starts from the page after doorbell / process_desc */ - base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, + base = kmap_atomic(i915_gem_object_get_page(gc->client->obj, (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT)); wq_off &= PAGE_SIZE - 1; wqi = (struct guc_wq_item *)((char *)base + wq_off); @@ -601,7 +599,7 @@ int i915_guc_submit(struct i915_guc_client *client, */ /** - * gem_allocate_guc_obj() - Allocate gem object for GuC usage + * guc_allocate_vma() - Allocate gem object for GuC usage * @dev: drm device * @size: size of object * @@ -611,46 +609,40 @@ int i915_guc_submit(struct i915_guc_client *client, * * Return: A drm_i915_gem_object if successful, otherwise NULL. */ -static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev, - u32 size) +static struct i915_vma *guc_allocate_vma(struct drm_device *dev, u32 size) { struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_gem_object *obj; + int ret; obj = i915_gem_alloc_object(dev, size); if (!obj) - return NULL; - - if (i915_gem_object_get_pages(obj)) { - drm_gem_object_unreference(&obj->base); - return NULL; - } + return ERR_PTR(-ENOMEM); - if (i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, - PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) { + ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, + PIN_OFFSET_BIAS | GUC_WOPCM_TOP); + if (ret) { drm_gem_object_unreference(&obj->base); - return NULL; + return ERR_PTR(ret); } /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); - return obj; + return i915_gem_obj_to_ggtt(obj); } /** - * gem_release_guc_obj() - Release gem object allocated for GuC usage - * @obj: gem obj to be released + * guc_release_vma() - Release gem object allocated for GuC usage + * @vma: gem obj to be released */ -static void gem_release_guc_obj(struct drm_i915_gem_object *obj) +static void guc_release_vma(struct i915_vma *vma) { - if (!obj) + if (vma == NULL) return; - if (i915_gem_obj_is_pinned(obj)) - i915_gem_object_ggtt_unpin(obj); - - drm_gem_object_unreference(&obj->base); + i915_vma_unpin(vma); + drm_gem_object_unreference(&vma->obj->base); } static void guc_client_free(struct drm_device *dev, @@ -677,7 +669,7 @@ static void guc_client_free(struct drm_device *dev, * Be sure to drop any locks */ - gem_release_guc_obj(client->client_obj); + guc_release_vma(client->client); if (client->ctx_index != GUC_INVALID_CTX_ID) { guc_fini_ctx_desc(guc, client); @@ -706,7 +698,7 @@ static struct i915_guc_client *guc_client_alloc(struct drm_device *dev, struct i915_guc_client *client; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_guc *guc = &dev_priv->guc; - struct drm_i915_gem_object *obj; + struct i915_vma *vma; client = kzalloc(sizeof(*client), GFP_KERNEL); if (!client) @@ -725,11 +717,11 @@ static struct i915_guc_client *guc_client_alloc(struct drm_device *dev, } /* The first page is doorbell/proc_desc. Two followed pages are wq. */ - obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE); - if (!obj) + vma = guc_allocate_vma(dev, GUC_DB_SIZE + GUC_WQ_SIZE); + if (IS_ERR(vma)) goto err; - client->client_obj = obj; + client->client = vma; client->wq_offset = GUC_DB_SIZE; client->wq_size = GUC_WQ_SIZE; @@ -774,7 +766,7 @@ err: static void guc_create_log(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); - struct drm_i915_gem_object *obj; + struct i915_vma *vma; unsigned long offset; uint32_t size, flags; @@ -790,16 +782,16 @@ static void guc_create_log(struct intel_guc *guc) GUC_LOG_ISR_PAGES + 1 + GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; - obj = guc->log_obj; - if (!obj) { - obj = gem_allocate_guc_obj(dev_priv->dev, size); - if (!obj) { + vma = guc->log; + if (vma == NULL) { + vma = guc_allocate_vma(dev_priv->dev, size); + if (IS_ERR(vma)) { /* logging will be off */ i915.guc_log_level = -1; return; } - guc->log_obj = obj; + guc->log = vma; } /* each allocated unit is a page */ @@ -808,7 +800,7 @@ static void guc_create_log(struct intel_guc *guc) (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); - offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */ + offset = vma->node.start >> PAGE_SHIFT; /* in pages */ guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; } @@ -837,7 +829,7 @@ static void init_guc_policies(struct guc_policies *policies) static void guc_create_ads(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); - struct drm_i915_gem_object *obj; + struct i915_vma *vma; struct guc_ads *ads; struct guc_policies *policies; struct guc_mmio_reg_state *reg_state; @@ -850,16 +842,16 @@ static void guc_create_ads(struct intel_guc *guc) sizeof(struct guc_mmio_reg_state) + GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; - obj = guc->ads_obj; - if (!obj) { - obj = gem_allocate_guc_obj(dev_priv->dev, PAGE_ALIGN(size)); - if (!obj) + vma = guc->ads; + if (vma == NULL) { + vma = guc_allocate_vma(dev_priv->dev, PAGE_ALIGN(size)); + if (IS_ERR(vma)) return; - guc->ads_obj = obj; + guc->ads = vma; } - page = i915_gem_object_get_page(obj, 0); + page = i915_gem_object_get_page(vma->obj, 0); ads = kmap(page); /* @@ -879,8 +871,7 @@ static void guc_create_ads(struct intel_guc *guc) policies = (void *)ads + sizeof(struct guc_ads); init_guc_policies(policies); - ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) + - sizeof(struct guc_ads); + ads->scheduler_policies = vma->node.start + sizeof(struct guc_ads); /* MMIO reg state */ reg_state = (void *)policies + sizeof(struct guc_policies); @@ -908,22 +899,22 @@ static void guc_create_ads(struct intel_guc *guc) */ int i915_guc_submission_init(struct drm_device *dev) { - struct drm_i915_private *dev_priv = dev->dev_private; - const size_t ctxsize = sizeof(struct guc_context_desc); - const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; - const size_t gemsize = round_up(poolsize, PAGE_SIZE); - struct intel_guc *guc = &dev_priv->guc; + struct intel_guc *guc = &to_i915(dev)->guc; + struct i915_vma *vma; + u32 size; if (!i915.enable_guc_submission) return 0; /* not enabled */ - if (guc->ctx_pool_obj) + if (guc->ctx_pool) return 0; /* already allocated */ - guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize); - if (!guc->ctx_pool_obj) - return -ENOMEM; + size = PAGE_ALIGN(GUC_MAX_GPU_CONTEXTS*sizeof(struct guc_context_desc)); + vma = guc_allocate_vma(dev, size); + if (IS_ERR(vma)) + return PTR_ERR(vma); + guc->ctx_pool = vma; ida_init(&guc->ctx_ids); guc_create_log(guc); @@ -966,19 +957,18 @@ void i915_guc_submission_disable(struct drm_device *dev) void i915_guc_submission_fini(struct drm_device *dev) { - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_guc *guc = &dev_priv->guc; + struct intel_guc *guc = &to_i915(dev)->guc; - gem_release_guc_obj(dev_priv->guc.ads_obj); - guc->ads_obj = NULL; + guc_release_vma(guc->ads); + guc->ads = NULL; - gem_release_guc_obj(dev_priv->guc.log_obj); - guc->log_obj = NULL; + guc_release_vma(guc->log); + guc->log = NULL; - if (guc->ctx_pool_obj) + if (guc->ctx_pool) ida_destroy(&guc->ctx_ids); - gem_release_guc_obj(guc->ctx_pool_obj); - guc->ctx_pool_obj = NULL; + guc_release_vma(guc->ctx_pool); + guc->ctx_pool = NULL; } /** diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 045b1491ff7a..9ea410614b3f 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -28,7 +28,7 @@ #include "i915_guc_reg.h" struct i915_guc_client { - struct drm_i915_gem_object *client_obj; + struct i915_vma *client; struct intel_context *owner; struct intel_guc *guc; uint32_t priority; @@ -87,11 +87,10 @@ struct intel_guc_fw { struct intel_guc { struct intel_guc_fw guc_fw; uint32_t log_flags; - struct drm_i915_gem_object *log_obj; + struct i915_vma *log; - struct drm_i915_gem_object *ads_obj; - - struct drm_i915_gem_object *ctx_pool_obj; + struct i915_vma *ads; + struct i915_vma *ctx_pool; struct ida ctx_ids; struct i915_guc_client *execbuf_client; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index dded672d5599..b447cfd58361 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -165,16 +165,15 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv) i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT; } - if (guc->ads_obj) { - u32 ads = (u32)i915_gem_obj_ggtt_offset(guc->ads_obj) - >> PAGE_SHIFT; + if (guc->ads) { + u32 ads = (u32)guc->ads->node.start >> PAGE_SHIFT; params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT; params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED; } /* If GuC submission is enabled, set up additional parameters here */ if (i915.enable_guc_submission) { - u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj); + u32 pgs = dev_priv->guc.ctx_pool->node.start; u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16; pgs >>= PAGE_SHIFT;