From patchwork Mon Jan 11 10:45:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8001601 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 35382BEEED for ; Mon, 11 Jan 2016 10:50:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3EF9720295 for ; Mon, 11 Jan 2016 10:50:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 571F720279 for ; Mon, 11 Jan 2016 10:50:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0D99E6E401; Mon, 11 Jan 2016 02:50:10 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by gabe.freedesktop.org (Postfix) with ESMTPS id B855C6E2D9 for ; Mon, 11 Jan 2016 02:47:09 -0800 (PST) Received: by mail-wm0-f67.google.com with SMTP id l65so25642189wmf.3 for ; Mon, 11 Jan 2016 02:47:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=V4S0tU+pI7DUabQ5gU3G/MPPWFNTkTnhFgum7Mzp3Z8=; b=uMA37Mcb9nvAMlbQPuufjLhwC64LVCVSMai9xT+NpO8vGTsKFC24s+rsqc5WP/kMQt Xz9KcxbyXMDsCTPon7ZCKttLho01UlVosYpO7XUeNwfEg8Xg16ribk8BE0o034fWw1p1 Ke7CazDCjuzBcU6uq5KbNAqD572XPEEBihwAFdDsrmyhVx/JFXK8w9kEi6mT0StJ4DaR q50+NxFdi5cpRUPkiXLtHCB8xmFlpRp/RBr3pY1WzxJaZu7u5qkbU2usb3WNTHMbD3z3 Y55/NBLsSJystoGQ7ex2ShiMzaCsPhBODwtIdlT4vyNgC54wUwWyt9YtfryvlSnV2WLj jYqA== X-Received: by 10.28.68.214 with SMTP id r205mr13509853wma.23.1452509228563; Mon, 11 Jan 2016 02:47:08 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id t3sm118879383wjz.11.2016.01.11.02.47.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 11 Jan 2016 02:47:07 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 11 Jan 2016 10:45:07 +0000 Message-Id: <1452509174-16671-37-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.7.0.rc3 In-Reply-To: <1452509174-16671-1-git-send-email-chris@chris-wilson.co.uk> References: <1452503961-14837-1-git-send-email-chris@chris-wilson.co.uk> <1452509174-16671-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 123/190] drm/i915: Mark unmappable GGTT entries as PIN_HIGH X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We allocate a few objects into the GGTT that we never need to access via the mappable aperture (such as contexts, status pages). We can request that these are bound high in the VM to increase the amount of mappable aperture available. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_context.c | 4 ++-- drivers/gpu/drm/i915/intel_lrc.c | 3 ++- drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++++++++---- 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 9250a7405807..c54c17944796 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -389,7 +389,7 @@ int i915_gem_context_init(struct drm_device *dev) * context. */ ret = i915_gem_object_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, - NULL, 0, alignment, 0); + NULL, 0, alignment, PIN_HIGH); if (ret) { DRM_ERROR("Failed to pinned default global context (error %d)\n", ret); @@ -677,7 +677,7 @@ static int do_switch(struct drm_i915_gem_request *req) if (engine->id == RCS) { u32 alignment = get_context_alignment(engine->dev); ret = i915_gem_object_ggtt_pin(to->legacy_hw_ctx.rcs_state, - NULL, 0, alignment, 0); + NULL, 0, alignment, PIN_HIGH); if (ret) return ret; } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 86fa41770ff1..206311b55e71 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -583,7 +583,8 @@ static int intel_lr_context_pin(struct intel_context *ctx, ctx_obj = ctx->engine[engine->id].state; ret = i915_gem_object_ggtt_pin(ctx_obj, NULL, 0, GEN8_LR_CONTEXT_ALIGN, - PIN_OFFSET_BIAS | GUC_WOPCM_TOP); + PIN_OFFSET_BIAS | GUC_WOPCM_TOP | + PIN_HIGH); if (ret) goto err; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ba3631d216fe..6db7f93a3c1d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -649,7 +649,8 @@ intel_init_pipe_control(struct intel_engine_cs *ring) if (ret) goto err_unref; - ret = i915_gem_object_ggtt_pin(ring->scratch.obj, NULL, 0, 4096, 0); + ret = i915_gem_object_ggtt_pin(ring->scratch.obj, NULL, + 0, 4096, PIN_HIGH); if (ret) goto err_unref; @@ -1891,7 +1892,9 @@ int intel_ring_map(struct intel_ring *ring) int ret; if (HAS_LLC(ring->engine->i915) && !obj->stolen) { - ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, 0); + ret = i915_gem_object_ggtt_pin(obj, NULL, + 0, PAGE_SIZE, + PIN_HIGH); if (ret) return ret; @@ -1906,7 +1909,8 @@ int intel_ring_map(struct intel_ring *ring) goto unpin; } } else { - ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, + ret = i915_gem_object_ggtt_pin(obj, NULL, + 0, PAGE_SIZE, PIN_MAPPABLE); if (ret) return ret; @@ -2505,7 +2509,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev) } else { i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); ret = i915_gem_object_ggtt_pin(obj, NULL, - 0, 0, 0); + 0, 0, + PIN_HIGH); if (ret != 0) { drm_gem_object_unreference(&obj->base); DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");