From patchwork Mon Jan 11 10:44:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8001661 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 997DDBEEE5 for ; Mon, 11 Jan 2016 10:50:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A7DFD2028D for ; Mon, 11 Jan 2016 10:50:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A919B20279 for ; Mon, 11 Jan 2016 10:50:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8021E6E465; Mon, 11 Jan 2016 02:50:38 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 95F326E2D1 for ; Mon, 11 Jan 2016 02:46:35 -0800 (PST) Received: by mail-wm0-f65.google.com with SMTP id f206so25660512wmf.2 for ; Mon, 11 Jan 2016 02:46:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=e0p0Fi/+e/qgwocqk0mIlcNzKMPoKtY6bVWi7skatIU=; b=puMFdvKQr6Z7x7znLG+z0fo5pQ2Aa5LUREdVswVT/KWag70DsZF2bYUti5GIAaLRSB uCr/+zjYivGtv84GGNlKZXMVRl/WxvlwuHAp9+P05GejoaWSGsf7JaV8kLlajsn1x0Bg AqD5dXx4eorpnQMh1S9P+2SOxvMI4A+ZFxPpBoM0PcKAySBNFvddjEB73WHJt9llKgsp mu0lwVb73MKJg1d4p4umq6Jd/RGOCc6Pf+RbSx14AhYeuXyVN3Lk1hf7ueYk44ksuVxD +Y1s7jNd37+BYLhCSmXUX9MM/BGmSWM1qJVcdtl+Xy0xYmAvFUJVM47/VtuQVsoYI0iG Ftkw== X-Received: by 10.28.182.135 with SMTP id g129mr13858387wmf.55.1452509194425; Mon, 11 Jan 2016 02:46:34 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id t3sm118879383wjz.11.2016.01.11.02.46.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 11 Jan 2016 02:46:33 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 11 Jan 2016 10:44:38 +0000 Message-Id: <1452509174-16671-8-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.7.0.rc3 In-Reply-To: <1452509174-16671-1-git-send-email-chris@chris-wilson.co.uk> References: <1452503961-14837-1-git-send-email-chris@chris-wilson.co.uk> <1452509174-16671-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 094/190] drm/i915: Remove early l3-remap X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since we do the l3-remap on context switch, and proceed to do a context switch immediately after manually doing the l3-remap, we can remove the redundant manual call. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_gem.c | 35 +-------------------------------- drivers/gpu/drm/i915/i915_gem_context.c | 30 +++++++++++++++++++++++++++- 3 files changed, 30 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f5f457920944..7dc3eed71eb3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2827,7 +2827,6 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); int __must_check i915_gem_init(struct drm_device *dev); int i915_gem_init_rings(struct drm_device *dev); int __must_check i915_gem_init_hw(struct drm_device *dev); -int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice); void i915_gem_init_swizzling(struct drm_device *dev); void i915_gem_cleanup_ringbuffer(struct drm_device *dev); int __must_check i915_gpu_idle(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 989222eb107b..379913221ab1 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3951,34 +3951,6 @@ err: return ret; } -int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) -{ - struct drm_i915_private *dev_priv = req->i915; - u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; - int i, ret; - - if (!HAS_L3_DPF(dev_priv) || !remap_info) - return 0; - - ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); - if (ret) - return ret; - - /* - * Note: We do not worry about the concurrent register cacheline hang - * here because no other code should access these registers other than - * at initialization time. - */ - for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { - intel_ring_emit(req->ring, MI_LOAD_REGISTER_IMM(1)); - intel_ring_emit_reg(req->ring, GEN7_L3LOG(slice, i)); - intel_ring_emit(req->ring, remap_info[i]); - } - intel_ring_advance(req->ring); - - return ret; -} - void i915_gem_init_swizzling(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4083,7 +4055,7 @@ i915_gem_init_hw(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *ring; - int ret, i, j; + int ret, i; if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) return -EIO; @@ -4158,11 +4130,6 @@ i915_gem_init_hw(struct drm_device *dev) goto out; } - if (ring->id == RCS) { - for (j = 0; j < NUM_L3_SLICES(dev); j++) - i915_gem_l3_remap(req, j); - } - ret = i915_ppgtt_init_ring(req); if (ret && ret != -EIO) { DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index e0ecfdfb0c8c..15e2e2abd72d 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -665,6 +665,34 @@ needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to, return false; } +static int remap_l3(struct drm_i915_gem_request *req, int slice) +{ + struct drm_i915_private *dev_priv = req->i915; + u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; + int i, ret; + + if (!HAS_L3_DPF(dev_priv) || !remap_info) + return 0; + + ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); + if (ret) + return ret; + + /* + * Note: We do not worry about the concurrent register cacheline hang + * here because no other code should access these registers other than + * at initialization time. + */ + for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { + intel_ring_emit(req->ring, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit_reg(req->ring, GEN7_L3LOG(slice, i)); + intel_ring_emit(req->ring, remap_info[i]); + } + intel_ring_advance(req->ring); + + return 0; +} + static int do_switch(struct drm_i915_gem_request *req) { struct intel_context *to = req->ctx; @@ -764,7 +792,7 @@ static int do_switch(struct drm_i915_gem_request *req) if (!(to->remap_slice & (1<