[3/3] ASoC: fsl_ssi: remove register defaults
diff mbox

Message ID CAOMZO5BE7=EdmEyMOq5WH=qv_0H3AGcyyDMJFoemLRJ=O5YLNw@mail.gmail.com
State New
Headers show

Commit Message

Fabio Estevam Jan. 11, 2016, 12:10 p.m. UTC
On Mon, Jan 11, 2016 at 10:04 AM, Fabio Estevam <festevam@gmail.com> wrote:

> This patch causes the following issue in linux-next:
>
> [    2.526984] ------------[ cut here ]------------
> [    2.531632] WARNING: CPU: 1 PID: 1 at kernel/locking/lockdep.c:2755
> lockdep_trace_alloc+0xf4/0x124()
> [    2.540771] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
> [    2.546175] Modules linked in:
> [    2.549447] CPU: 1 PID: 1 Comm: swapper/0 Not tainted
> 4.4.0-rc8-next-20160111 #204
> [    2.557021] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
> [    2.563553] Backtrace:
> [    2.566040] [<c00136d8>] (dump_backtrace) from [<c0013874>]
> (show_stack+0x18/0x1c)
> [    2.573615]  r6:00000ac3 r5:00000000 r4:00000000 r3:00000000
> [    2.579362] [<c001385c>] (show_stack) from [<c02de89c>]
> (dump_stack+0x88/0xa4)
> [    2.586607] [<c02de814>] (dump_stack) from [<c002bcac>]
> (warn_slowpath_common+0x80/0xbc)
> [    2.594702]  r5:c0071ed0 r4:ef055b90
> [    2.598326] [<c002bc2c>] (warn_slowpath_common) from [<c002bd8c>]
> (warn_slowpath_fmt+0x38/0x40)
> [    2.607028]  r8:00000004 r7:00000004 r6:024080c0 r5:024080c0 r4:60000093
> [    2.613829] [<c002bd58>] (warn_slowpath_fmt) from [<c0071ed0>]
> (lockdep_trace_alloc+0xf4/0x124)
> [    2.622532]  r3:c09a1634 r2:c099dc0c
> [    2.626161] [<c0071ddc>] (lockdep_trace_alloc) from [<c010bc0c>]
> (kmem_cache_alloc+0x30/0x174)
> [    2.634778]  r4:ef001f00 r3:c0b02a88
> [    2.638407] [<c010bbdc>] (kmem_cache_alloc) from [<c03edac8>]
> (regcache_rbtree_write+0x150/0x724)
> [    2.647283]  r10:00000000 r9:00000010 r8:00000004 r7:00000004
> r6:0000002c r5:00000000
> [    2.655203]  r4:00000000
> [    2.657767] [<c03ed978>] (regcache_rbtree_write) from [<c03ec7d8>]
> (regcache_write+0x5c/0x64)

This fixes the warning:

Comments

Maciej S. Szmigiero Jan. 11, 2016, 1:57 p.m. UTC | #1
Hi Fabio,

Thanks for testing.

On 11.01.2016 13:10, Fabio Estevam wrote:
> On Mon, Jan 11, 2016 at 10:04 AM, Fabio Estevam <festevam@gmail.com> wrote:
> 
>> This patch causes the following issue in linux-next:
>>
>> [    2.526984] ------------[ cut here ]------------
>> [    2.531632] WARNING: CPU: 1 PID: 1 at kernel/locking/lockdep.c:2755
>> lockdep_trace_alloc+0xf4/0x124()
>> [    2.540771] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
>> [    2.546175] Modules linked in:
>> [    2.549447] CPU: 1 PID: 1 Comm: swapper/0 Not tainted
>> 4.4.0-rc8-next-20160111 #204
>> [    2.557021] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
>> [    2.563553] Backtrace:
>> [    2.566040] [<c00136d8>] (dump_backtrace) from [<c0013874>]
>> (show_stack+0x18/0x1c)
>> [    2.573615]  r6:00000ac3 r5:00000000 r4:00000000 r3:00000000
>> [    2.579362] [<c001385c>] (show_stack) from [<c02de89c>]
>> (dump_stack+0x88/0xa4)
>> [    2.586607] [<c02de814>] (dump_stack) from [<c002bcac>]
>> (warn_slowpath_common+0x80/0xbc)
>> [    2.594702]  r5:c0071ed0 r4:ef055b90
>> [    2.598326] [<c002bc2c>] (warn_slowpath_common) from [<c002bd8c>]
>> (warn_slowpath_fmt+0x38/0x40)
>> [    2.607028]  r8:00000004 r7:00000004 r6:024080c0 r5:024080c0 r4:60000093
>> [    2.613829] [<c002bd58>] (warn_slowpath_fmt) from [<c0071ed0>]
>> (lockdep_trace_alloc+0xf4/0x124)
>> [    2.622532]  r3:c09a1634 r2:c099dc0c
>> [    2.626161] [<c0071ddc>] (lockdep_trace_alloc) from [<c010bc0c>]
>> (kmem_cache_alloc+0x30/0x174)
>> [    2.634778]  r4:ef001f00 r3:c0b02a88
>> [    2.638407] [<c010bbdc>] (kmem_cache_alloc) from [<c03edac8>]
>> (regcache_rbtree_write+0x150/0x724)
>> [    2.647283]  r10:00000000 r9:00000010 r8:00000004 r7:00000004
>> r6:0000002c r5:00000000
>> [    2.655203]  r4:00000000
>> [    2.657767] [<c03ed978>] (regcache_rbtree_write) from [<c03ec7d8>]
>> (regcache_write+0x5c/0x64)
> 
> This fixes the warning:
> 
> --- a/sound/soc/fsl/fsl_ssi.c
> +++ b/sound/soc/fsl/fsl_ssi.c
> @@ -180,7 +180,6 @@ static const struct regmap_config fsl_ssi_regconfig = {
>         .volatile_reg = fsl_ssi_volatile_reg,
>         .precious_reg = fsl_ssi_precious_reg,
>         .writeable_reg = fsl_ssi_writeable_reg,
> -       .cache_type = REGCACHE_RBTREE,
>  };
> 
> Is this the correct fix?
> 

This will disable register cache so it isn't right.
Could you try REGCACHE_FLAT instead, please?

Looks like the problem here is rbtree cache does some non-atomic allocations in
read / write path when not supplied with default register values.

Best regards,
Maciej Szmigiero
Mark Brown Jan. 11, 2016, 2 p.m. UTC | #2
On Mon, Jan 11, 2016 at 10:10:56AM -0200, Fabio Estevam wrote:
> On Mon, Jan 11, 2016 at 10:04 AM, Fabio Estevam <festevam@gmail.com> wrote:

> > [    2.526984] ------------[ cut here ]------------
> > [    2.531632] WARNING: CPU: 1 PID: 1 at kernel/locking/lockdep.c:2755
> > lockdep_trace_alloc+0xf4/0x124()

> This fixes the warning:

> --- a/sound/soc/fsl/fsl_ssi.c
> +++ b/sound/soc/fsl/fsl_ssi.c
> @@ -180,7 +180,6 @@ static const struct regmap_config fsl_ssi_regconfig = {
>         .volatile_reg = fsl_ssi_volatile_reg,
>         .precious_reg = fsl_ssi_precious_reg,
>         .writeable_reg = fsl_ssi_writeable_reg,
> -       .cache_type = REGCACHE_RBTREE,
>  };

> Is this the correct fix?

I suspect not, it looks like the driver is using the cache for
suspend/resume handling.  I've dropped the patch for now.  Either the
driver should explicitly write to the relevant registers outside of
interrupt context to ensure the cache entry exists or it should keep the
defaults and explicitly write them to hardware at startup to ensure
sync (the former is more likely to be safe).
Fabio Estevam Jan. 11, 2016, 2:05 p.m. UTC | #3
Hi Maciej,

On Mon, Jan 11, 2016 at 11:57 AM, Maciej S. Szmigiero
<mail@maciej.szmigiero.name> wrote:
> Hi Fabio,

> This will disable register cache so it isn't right.
> Could you try REGCACHE_FLAT instead, please?

Yes, with REGCACHE_FLAT I don't get the warning.

Regards,

Fabio Estevam
Maciej S. Szmigiero Jan. 11, 2016, 2:10 p.m. UTC | #4
On 11.01.2016 15:00, Mark Brown wrote:
> On Mon, Jan 11, 2016 at 10:10:56AM -0200, Fabio Estevam wrote:
>> On Mon, Jan 11, 2016 at 10:04 AM, Fabio Estevam <festevam@gmail.com> wrote:
> 
>>> [    2.526984] ------------[ cut here ]------------
>>> [    2.531632] WARNING: CPU: 1 PID: 1 at kernel/locking/lockdep.c:2755
>>> lockdep_trace_alloc+0xf4/0x124()
> 
>> This fixes the warning:
> 
>> --- a/sound/soc/fsl/fsl_ssi.c
>> +++ b/sound/soc/fsl/fsl_ssi.c
>> @@ -180,7 +180,6 @@ static const struct regmap_config fsl_ssi_regconfig = {
>>         .volatile_reg = fsl_ssi_volatile_reg,
>>         .precious_reg = fsl_ssi_precious_reg,
>>         .writeable_reg = fsl_ssi_writeable_reg,
>> -       .cache_type = REGCACHE_RBTREE,
>>  };
> 
>> Is this the correct fix?
> 
> I suspect not, it looks like the driver is using the cache for
> suspend/resume handling.  I've dropped the patch for now.  Either the
> driver should explicitly write to the relevant registers outside of
> interrupt context to ensure the cache entry exists or it should keep the
> defaults and explicitly write them to hardware at startup to ensure
> sync (the former is more likely to be safe).

Is it acceptable to switch it to flat cache instead to not keep the register
defaults in driver?

Maciej
Mark Brown Jan. 11, 2016, 2:54 p.m. UTC | #5
On Mon, Jan 11, 2016 at 03:10:20PM +0100, Maciej S. Szmigiero wrote:
> On 11.01.2016 15:00, Mark Brown wrote:

> > I suspect not, it looks like the driver is using the cache for
> > suspend/resume handling.  I've dropped the patch for now.  Either the
> > driver should explicitly write to the relevant registers outside of
> > interrupt context to ensure the cache entry exists or it should keep the
> > defaults and explicitly write them to hardware at startup to ensure
> > sync (the former is more likely to be safe).

> Is it acceptable to switch it to flat cache instead to not keep the register
> defaults in driver?

That's possibly problematic because the flat cache will of necessity end
up with defaults (of 0 from the kzalloc()) for all the registers.
You'll still have default values in the cache, though some of the
behaviour around optimising syncs does change without them explicitly
given.  It does deal with the allocation issue but given that the issue
was incorrect defaults I'd be a bit concerned.
Timur Tabi Jan. 11, 2016, 3:45 p.m. UTC | #6
Mark Brown wrote:
> That's possibly problematic because the flat cache will of necessity end
> up with defaults (of 0 from the kzalloc()) for all the registers.
> You'll still have default values in the cache, though some of the
> behaviour around optimising syncs does change without them explicitly
> given.  It does deal with the allocation issue but given that the issue
> was incorrect defaults I'd be a bit concerned.

Ok, I'm confused.  Granted, all of this regcache stuff was added after I 
stopped working on this driver, so I'm out of the loop.  But it appears 
that the regcache cannot properly handle an uninitialized cache.  I 
would expect it to know to perform hard reads of any registers that are 
uninitialized.

If the regcache wants to have an initialized cache, then it should 
automatically perform reads an all non-volatile, non-precious registers 
at initialization.
Mark Brown Jan. 11, 2016, 4:12 p.m. UTC | #7
On Mon, Jan 11, 2016 at 09:45:37AM -0600, Timur Tabi wrote:

> Ok, I'm confused.  Granted, all of this regcache stuff was added after I
> stopped working on this driver, so I'm out of the loop.  But it appears that
> the regcache cannot properly handle an uninitialized cache.  I would expect
> it to know to perform hard reads of any registers that are uninitialized.

regcache handles this fine, it's perfectly happy to just go and allocate
the cache as registers get used (this is why the code that's doing the
allocation exists...).  What is causing problems here is that the first
access to the register is happening in interrupt context so we can't do
a GFP_KERNEL allocation for it.  Most users don't do anything at all in
interrupt context so it's not an issue for them, drivers that want to
use regmap in interrupt context need to handle this.

We can't rely on knowing which registers are valid and which registers
can be read without side effects, it's optional for drivers to provide
that information.  Even with that information it's not always clear that
we want to stop and read every single value when we are initialising the
device, that might be excessively slow (remember a lot of regmap devices
are I2C or SPI connected, some with large register maps).  We should
have a helper to do that though for drivers where it does make sense.
Timur Tabi Jan. 12, 2016, 1:23 a.m. UTC | #8
Mark Brown wrote:
> regcache handles this fine, it's perfectly happy to just go and allocate
> the cache as registers get used (this is why the code that's doing the
> allocation exists...).  What is causing problems here is that the first
> access to the register is happening in interrupt context so we can't do
> a GFP_KERNEL allocation for it.

Considering how small and not-sparse the SSI register space is, would 
using REGCACHE_FLAT be appropriate?
Mark Brown Jan. 12, 2016, 1:34 a.m. UTC | #9
On Mon, Jan 11, 2016 at 07:23:54PM -0600, Timur Tabi wrote:
> Mark Brown wrote:

> >regcache handles this fine, it's perfectly happy to just go and allocate
> >the cache as registers get used (this is why the code that's doing the
> >allocation exists...).  What is causing problems here is that the first
> >access to the register is happening in interrupt context so we can't do
> >a GFP_KERNEL allocation for it.

> Considering how small and not-sparse the SSI register space is, would using
> REGCACHE_FLAT be appropriate?

Quite possibly (it'll be more efficient and it's intended for such use
cases) but as I said in my other reply that then has the issue that it
implicitly gives default values to all the registers so I'd expect we
still need to handle the cache initialisation explicitly (or
alternatively the hardware sync with the cache on startup).
Timur Tabi Jan. 12, 2016, 1:53 a.m. UTC | #10
Mark Brown wrote:
> Quite possibly (it'll be more efficient and it's intended for such use
> cases) but as I said in my other reply that then has the issue that it
> implicitly gives default values to all the registers so I'd expect we
> still need to handle the cache initialisation explicitly (or
> alternatively the hardware sync with the cache on startup).

Why does REGCACHE_FLAT assume that all registers have a default value of 
0?  Shouldn't it have the same behavior w.r.t. cache values as 
REGCACHE_RBTREE?

Patch
diff mbox

--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -180,7 +180,6 @@  static const struct regmap_config fsl_ssi_regconfig = {
        .volatile_reg = fsl_ssi_volatile_reg,
        .precious_reg = fsl_ssi_precious_reg,
        .writeable_reg = fsl_ssi_writeable_reg,
-       .cache_type = REGCACHE_RBTREE,
 };

Is this the correct fix?