drm/i915: Codify our assumption that the Global GTT is <= 4GiB
diff mbox

Message ID 1452853211-23959-1-git-send-email-chris@chris-wilson.co.uk
State New
Headers show

Commit Message

Chris Wilson Jan. 15, 2016, 10:20 a.m. UTC
Throughout the code base, we use u32 for offsets into the global GTT. If
we ever see any hardware with a larger GGTT, then we run the real risk
of silent corruption. So test for our assumption up front so that we
have a nice reminder should the time come when it fails.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Dave Gordon Jan. 15, 2016, 11:25 a.m. UTC | #1
On 15/01/16 10:20, Chris Wilson wrote:
> Throughout the code base, we use u32 for offsets into the global GTT. If
> we ever see any hardware with a larger GGTT, then we run the real risk
> of silent corruption. So test for our assumption up front so that we
> have a nice reminder should the time come when it fails.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> ---
>   drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 2e460b369e82..0d910638972c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3143,6 +3143,13 @@ int i915_gem_gtt_init(struct drm_device *dev)
>   	if (ret)
>   		return ret;
>
> +	if ((gtt->base.total - 1) >> 32) {
> +		DRM_ERROR("We never expected a Global GTT with more than 32bits of address space! Found %lldM!\n",
> +			  gtt->base.total >> 20);
> +		gtt->base.total = 1ull << 32;
> +		gtt->mappable_end = min(gtt->mappable_end, gtt->base.total);

Assuming Mika's comment on 'struct i915_address_space' is correct:
...
	u64 start;              /* Start offset always 0 for dri2 */
...
otherwise this calculation would need to be adjusted.

> +
>   	/* GMADR is the PCI mmio aperture into the global GTT. */
>   	DRM_INFO("Memory usable by graphics device = %lluM\n",
>   		 gtt->base.total >> 20);

LGTM.

Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Chris Wilson Jan. 15, 2016, 11:28 a.m. UTC | #2
On Fri, Jan 15, 2016 at 10:20:11AM +0000, Chris Wilson wrote:
> Throughout the code base, we use u32 for offsets into the global GTT. If
> we ever see any hardware with a larger GGTT, then we run the real risk
> of silent corruption. So test for our assumption up front so that we
> have a nice reminder should the time come when it fails.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>

From the earlier cut-n-paste,

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

(so I hope it still holds with the minor correction applied :)
-Chris
Chris Wilson Jan. 15, 2016, 11:52 a.m. UTC | #3
On Fri, Jan 15, 2016 at 11:25:38AM +0000, Dave Gordon wrote:
> On 15/01/16 10:20, Chris Wilson wrote:
> >Throughout the code base, we use u32 for offsets into the global GTT. If
> >we ever see any hardware with a larger GGTT, then we run the real risk
> >of silent corruption. So test for our assumption up front so that we
> >have a nice reminder should the time come when it fails.
> >
> >Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >Cc: Daniel Vetter <daniel@ffwll.ch>
> >---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >index 2e460b369e82..0d910638972c 100644
> >--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> >+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >@@ -3143,6 +3143,13 @@ int i915_gem_gtt_init(struct drm_device *dev)
> >  	if (ret)
> >  		return ret;
> >
> >+	if ((gtt->base.total - 1) >> 32) {
> >+		DRM_ERROR("We never expected a Global GTT with more than 32bits of address space! Found %lldM!\n",
> >+			  gtt->base.total >> 20);
> >+		gtt->base.total = 1ull << 32;
> >+		gtt->mappable_end = min(gtt->mappable_end, gtt->base.total);
> 
> Assuming Mika's comment on 'struct i915_address_space' is correct:
> ...
> 	u64 start;              /* Start offset always 0 for dri2 */
> ...
> otherwise this calculation would need to be adjusted.

The address_space start was for the obsolete UMS call where the xserver
would tell the kernel the range of the (then only global) GTT to use for
itself.

The vgpu plugin comes later? Though if I remember correctly, it reserves
ranges of the GGTT for itself rather than alter the drm_mm.

So I don't think it has been revitalised since. Removing the start value
from the struct i915_address_space confirms it is obsolete.
-Chris
Ville Syrjälä Jan. 15, 2016, 12:49 p.m. UTC | #4
On Fri, Jan 15, 2016 at 11:28:16AM +0000, Chris Wilson wrote:
> On Fri, Jan 15, 2016 at 10:20:11AM +0000, Chris Wilson wrote:
> > Throughout the code base, we use u32 for offsets into the global GTT. If
> > we ever see any hardware with a larger GGTT, then we run the real risk
> > of silent corruption. So test for our assumption up front so that we
> > have a nice reminder should the time come when it fails.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> 
> >From the earlier cut-n-paste,
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> (so I hope it still holds with the minor correction applied :)

Yes. Please excuse the sucky review I gave to the original.

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2e460b369e82..0d910638972c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3143,6 +3143,13 @@  int i915_gem_gtt_init(struct drm_device *dev)
 	if (ret)
 		return ret;
 
+	if ((gtt->base.total - 1) >> 32) {
+		DRM_ERROR("We never expected a Global GTT with more than 32bits of address space! Found %lldM!\n",
+			  gtt->base.total >> 20);
+		gtt->base.total = 1ull << 32;
+		gtt->mappable_end = min(gtt->mappable_end, gtt->base.total);
+	}
+
 	/* GMADR is the PCI mmio aperture into the global GTT. */
 	DRM_INFO("Memory usable by graphics device = %lluM\n",
 		 gtt->base.total >> 20);