From patchwork Fri Jan 15 13:53:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8041131 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 42618BEEE5 for ; Fri, 15 Jan 2016 13:53:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1CE0C203B4 for ; Fri, 15 Jan 2016 13:53:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2CBBE2044B for ; Fri, 15 Jan 2016 13:53:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 080C16EB71; Fri, 15 Jan 2016 05:53:41 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id CFFF26EB71 for ; Fri, 15 Jan 2016 05:53:39 -0800 (PST) Received: by mail-wm0-f65.google.com with SMTP id f206so2976298wmf.2 for ; Fri, 15 Jan 2016 05:53:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=sJ+IN23wJJqWPlFS6CNCzo1juSjn69XAr3CqSFfbNX8=; b=JWJvH28nyUE6Jx+DAgaIYkeMfrSjaMS8HKtkGb8EbtVpCWRSE5Z+5mfS8MH30E3wFs DcEcF4pt+hV7F6jFZZVUX+211T8e0BKVY6jNQtEU6bAKp1iM2mdRKkU/4OqxJFZ4WfZW eLrUhTzE1saSX3ZQXWvqCMb85Wj/vGHXzUynVDDqzK6Tpn9GjXH7tKjAXz1M2lQNsEZi V75jxe+xb/SAlSwquzvhfUU9T0e9wrn+Jtyi+SP5NKYlZ1QE3ffIuHvnkrSnNdvypEnF X4v4gVqf2qKjg4hj3s8hNHI+q0NtkDNzUohJEt6vYAVmYyauVyjiLigdN+UAKaWG9noT dAGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-type :content-transfer-encoding; bh=sJ+IN23wJJqWPlFS6CNCzo1juSjn69XAr3CqSFfbNX8=; b=RIA51zdJ6LiKqyJeiFeMdjQb6Mj4aqRMnAq/KN2WNhNGP5UlguyDOySjnFjTSYmxkm Q4MnJ0tYZhD+nMgpBz1u2VH/dv6cTea76dY0IAPhQbDG83KcqrdzXtmQGxgsRIheQtg/ wJukbHcAI3azJF8I5eAwxM8CfTKeVGEc6cIPVx+euKbvkRH2dLdDzss3hUcLsRRH+FNU PRIy0wsXJLspokkoBhc9ZrFVby7Ahtz3vXIylF/ZtAYgjZaH+OIbM1izepPL0AMr843m iuBZqhY4Hok7yqrTj1UQrCdpwMA70Fen7b8Y/tHQMod7rYDvooxu2ZiAahXXBzeAVI/J DBsw== X-Gm-Message-State: AG10YORUkNI1itQiNbT7ntOTha+cdKu6qnFUpw+H+mHSq6Te8Stnd5Yz798BKtAfSgsSkg== X-Received: by 10.28.128.215 with SMTP id b206mr3840647wmd.52.1452866017952; Fri, 15 Jan 2016 05:53:37 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id bg1sm6415324wjc.27.2016.01.15.05.53.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 15 Jan 2016 05:53:36 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 15 Jan 2016 13:53:23 +0000 Message-Id: <1452866003-17538-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.7.0.rc3 In-Reply-To: <20160115122730.GG8308@nuc-i3427.alporthouse.com> References: <20160115122730.GG8308@nuc-i3427.alporthouse.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH igt] tests: Add gem_busy X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exercise the busy-ioctl and verify it reports the right active engines using the execbuffer notation. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- tests/Makefile.sources | 1 + tests/gem_busy.c | 233 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 234 insertions(+) create mode 100644 tests/gem_busy.c diff --git a/tests/Makefile.sources b/tests/Makefile.sources index d2c7d6f..545aca0 100644 --- a/tests/Makefile.sources +++ b/tests/Makefile.sources @@ -11,6 +11,7 @@ TESTS_progs_M = \ drv_hangman \ gem_bad_reloc \ gem_basic \ + gem_busy \ gem_caching \ gem_close_race \ gem_concurrent_blit \ diff --git a/tests/gem_busy.c b/tests/gem_busy.c new file mode 100644 index 0000000..c6b8a8b --- /dev/null +++ b/tests/gem_busy.c @@ -0,0 +1,233 @@ +/* + * Copyright © 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "igt.h" + +/* Exercise the busy-ioctl, ensuring the ABI is never broken */ +IGT_TEST_DESCRIPTION("Basic check of busy-ioctl ABI."); + +enum { TEST = 0, BUSY, BATCH }; + +static void __gem_busy(int fd, + uint32_t handle, + uint32_t *read, + uint32_t *write) +{ + struct drm_i915_gem_busy busy; + + memset(&busy, 0, sizeof(busy)); + busy.handle = handle; + + do_ioctl(fd, DRM_IOCTL_I915_GEM_BUSY, &busy); + + *write = busy.busy & 0xffff; + *read = busy.busy >> 16; +} + +static uint32_t busy_blt(int fd) +{ + const int gen = intel_gen(intel_get_drm_devid(fd)); + const int has_64bit_reloc = gen >= 8; + struct drm_i915_gem_execbuffer2 execbuf; + struct drm_i915_gem_exec_object2 object[2]; + struct drm_i915_gem_relocation_entry reloc[20], *r; + uint32_t read, write; + uint32_t *map; + int factor = 10; + int i = 0; + + memset(object, 0, sizeof(object)); + object[0].handle = gem_create(fd, 1024*1024); + object[1].handle = gem_create(fd, 4096); + + r = memset(reloc, 0, sizeof(reloc)); + map = gem_mmap__cpu(fd, object[1].handle, 0, 4096, PROT_WRITE); + gem_set_domain(fd, object[1].handle, + I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU); + +#define COPY_BLT_CMD (2<<29|0x53<<22|0x6) +#define BLT_WRITE_ALPHA (1<<21) +#define BLT_WRITE_RGB (1<<20) + while (factor--) { + /* XY_SRC_COPY */ + map[i++] = COPY_BLT_CMD | BLT_WRITE_ALPHA | BLT_WRITE_RGB; + if (has_64bit_reloc) + map[i-1] += 2; + map[i++] = 0xcc << 16 | 1 << 25 | 1 << 24 | (4*1024); + map[i++] = 0; + map[i++] = 256 << 16 | 1024; + + r->offset = i * sizeof(uint32_t); + r->target_handle = object[0].handle; + r->read_domains = I915_GEM_DOMAIN_RENDER; + r->write_domain = I915_GEM_DOMAIN_RENDER; + r++; + map[i++] = 0; + if (has_64bit_reloc) + map[i++] = 0; + + map[i++] = 0; + map[i++] = 4096; + + r->offset = i * sizeof(uint32_t); + r->target_handle = object[0].handle; + r->read_domains = I915_GEM_DOMAIN_RENDER; + r->write_domain = 0; + r++; + map[i++] = 0; + if (has_64bit_reloc) + map[i++] = 0; + } + map[i++] = MI_BATCH_BUFFER_END; + munmap(map, 4096); + + object[1].relocs_ptr = (uintptr_t)reloc; + object[1].relocation_count = r - reloc; + + memset(&execbuf, 0, sizeof(execbuf)); + execbuf.buffers_ptr = (unsigned long)object; + execbuf.buffer_count = 2; + if (gen >= 6) + execbuf.flags = I915_EXEC_BLT; + gem_execbuf(fd, &execbuf); + + __gem_busy(fd, object[0].handle, &read, &write); + igt_assert_eq(read, 1 << write); + igt_assert_eq(write, gen >= 6 ? I915_EXEC_BLT : I915_EXEC_RENDER); + + igt_debug("Created busy handle %d\n", object[0].handle); + gem_close(fd, object[1].handle); + return object[0].handle; +} + +static int __gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb) +{ + int err = 0; + if (drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, eb)) + err = -errno; + return err; +} + +static bool exec_noop(int fd, + uint32_t *handles, + unsigned ring, + bool write) +{ + struct drm_i915_gem_execbuffer2 execbuf; + struct drm_i915_gem_exec_object2 exec[3]; + + memset(exec, 0, sizeof(exec)); + exec[0].handle = handles[BUSY]; + exec[1].handle = handles[TEST]; + if (write) + exec[1].flags |= EXEC_OBJECT_WRITE; + exec[2].handle = handles[BATCH]; + + memset(&execbuf, 0, sizeof(execbuf)); + execbuf.buffers_ptr = (uintptr_t)exec; + execbuf.buffer_count = 3; + execbuf.flags = ring; + igt_debug("Queuing handle for %s on ring %d\n", + write ? "writing" : "reading", ring & 0x7); + return __gem_execbuf(fd, &execbuf) == 0; +} + +static void test_ring(int fd, unsigned ring, uint32_t flags) +{ + uint32_t bbe = MI_BATCH_BUFFER_END; + uint32_t handle[3]; + uint32_t read, write; + uint32_t active; + unsigned i; + + handle[TEST] = gem_create(fd, 4096); + handle[BATCH] = gem_create(fd, 4096); + gem_write(fd, handle[BATCH], 0, &bbe, sizeof(bbe)); + + /* Create a long running batch which we can use to hog the GPU */ + handle[BUSY] = busy_blt(fd); + + /* Queue a batch after the busy, it should block and remain "busy" */ + igt_require(exec_noop(fd, handle, ring | flags, false)); + __gem_busy(fd, handle[TEST], &read, &write); + igt_assert_eq(read, 1 << ring); + igt_assert_eq(write, 0); + + /* Now queue it on all available rings, and set it as write on this */ + active = 0; + for (i = I915_EXEC_RENDER; i <= I915_EXEC_VEBOX; i++) { + if (exec_noop(fd, handle, i | flags, i == ring)) + active |= 1 << i; + } + __gem_busy(fd, handle[TEST], &read, &write); + igt_assert_eq(read, active); + igt_assert_eq(write, ring); + + /* Check that our long batch was long enough */ + __gem_busy(fd, handle[BUSY], &read, &write); + igt_assert(write); + + for (i = TEST; i <= BATCH; i++) + gem_close(fd, handle[i]); +} + +static bool has_semaphores(int fd) +{ + struct drm_i915_getparam gp; + int val = -1; + + memset(&gp, 0, sizeof(gp)); + gp.param = I915_PARAM_HAS_SEMAPHORES; + gp.value = &val; + + drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp); + errno = 0; + + return val > 0; +} + +igt_main +{ + int fd = -1; + + igt_skip_on_simulation(); + + igt_fixture { + fd = drm_open_driver(DRIVER_INTEL); + igt_require(has_semaphores(fd)); + } + + igt_subtest("render") + test_ring(fd, I915_EXEC_RENDER, 0); + igt_subtest("bsd") + test_ring(fd, I915_EXEC_BSD, 1<<13 /*I915_EXEC_BSD_RING1*/); + igt_subtest("bsd2") + test_ring(fd, I915_EXEC_BSD, 2<<13 /*I915_EXEC_BSD_RING2*/); + igt_subtest("blt") + test_ring(fd, I915_EXEC_BLT, 0); + igt_subtest("vebox") + test_ring(fd, I915_EXEC_VEBOX, 0); + + igt_fixture + close(fd); +}