| Message ID | 1453889591-30968-11-git-send-email-david@gibson.dropbear.id.au (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 2016-01-27 at 21:13 +1100, David Gibson wrote: > Now that the TCG and spapr code has been extended to allow (semi-) > arbitrary page encodings in the CPU's 'sps' table, we can add the > many > page sizes supported by real POWER7 and POWER8 hardware that we > previously > didn't support in TCG. > > Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> > --- > target-ppc/mmu-hash64.h | 2 ++ > target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++ > 2 files changed, 34 insertions(+) > > diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h > index 34cf975..ab0f86b 100644 > --- a/target-ppc/mmu-hash64.h > +++ b/target-ppc/mmu-hash64.h > @@ -48,6 +48,8 @@ unsigned > ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, > #define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP) > #define SLB_VSID_4K 0x0000000000000000ULL > #define SLB_VSID_64K 0x0000000000000110ULL > +#define SLB_VSID_16M 0x0000000000000100ULL > +#define SLB_VSID_16G 0x0000000000000120ULL > > /* > * Hash page table definitions > diff --git a/target-ppc/translate_init.c b/target- > ppc/translate_init.c > index f6babd2..32b3679 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -8104,6 +8104,36 @@ static Property powerpc_servercpu_properties[] > = { > DEFINE_PROP_END_OF_LIST(), > }; > > +#ifdef CONFIG_SOFTMMU > +static const struct ppc_segment_page_sizes POWER7_POWER8_sps = { > + .sps = { > + { > + .page_shift = 12, /* 4K */ > + .slb_enc = 0, > + .enc = { { .page_shift = 12, .pte_enc = 0 }, > + { .page_shift = 16, .pte_enc = 0x7 }, > + { .page_shift = 24, .pte_enc = 0x38 }, }, > + }, > + { > + .page_shift = 16, /* 64K */ > + .slb_enc = SLB_VSID_64K, > + .enc = { { .page_shift = 16, .pte_enc = 0x1 }, > + { .page_shift = 24, .pte_enc = 0x8 }, }, > + }, > + { > + .page_shift = 24, /* 16M */ > + .slb_enc = SLB_VSID_16M, > + .enc = { { .page_shift = 24, .pte_enc = 0 }, }, > + }, > + { > + .page_shift = 34, /* 16G */ > + .slb_enc = SLB_VSID_16G, > + .enc = { { .page_shift = 34, .pte_enc = 0x3 }, }, > + }, > + } > +}; > > +#endif /* CONFIG_SOFTMMU */ > + > static void init_proc_POWER7 (CPUPPCState *env) > { > init_proc_book3s_64(env, BOOK3S_CPU_POWER7); > @@ -8167,6 +8197,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void > *data) > pcc->mmu_model = POWERPC_MMU_2_06; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; > + pcc->sps = &POWER7_POWER8_sps; > #endif > pcc->excp_model = POWERPC_EXCP_POWER7; > pcc->bus_model = PPC_FLAGS_INPUT_POWER7; > @@ -8247,6 +8278,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void > *data) > pcc->mmu_model = POWERPC_MMU_2_07; > #if defined(CONFIG_SOFTMMU) > pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; > + pcc->sps = &POWER7_POWER8_sps; > #endif > pcc->excp_model = POWERPC_EXCP_POWER7; > pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 34cf975..ab0f86b 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -48,6 +48,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, #define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP) #define SLB_VSID_4K 0x0000000000000000ULL #define SLB_VSID_64K 0x0000000000000110ULL +#define SLB_VSID_16M 0x0000000000000100ULL +#define SLB_VSID_16G 0x0000000000000120ULL /* * Hash page table definitions diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index f6babd2..32b3679 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8104,6 +8104,36 @@ static Property powerpc_servercpu_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +#ifdef CONFIG_SOFTMMU +static const struct ppc_segment_page_sizes POWER7_POWER8_sps = { + .sps = { + { + .page_shift = 12, /* 4K */ + .slb_enc = 0, + .enc = { { .page_shift = 12, .pte_enc = 0 }, + { .page_shift = 16, .pte_enc = 0x7 }, + { .page_shift = 24, .pte_enc = 0x38 }, }, + }, + { + .page_shift = 16, /* 64K */ + .slb_enc = SLB_VSID_64K, + .enc = { { .page_shift = 16, .pte_enc = 0x1 }, + { .page_shift = 24, .pte_enc = 0x8 }, }, + }, + { + .page_shift = 24, /* 16M */ + .slb_enc = SLB_VSID_16M, + .enc = { { .page_shift = 24, .pte_enc = 0 }, }, + }, + { + .page_shift = 34, /* 16G */ + .slb_enc = SLB_VSID_16G, + .enc = { { .page_shift = 34, .pte_enc = 0x3 }, }, + }, + } +}; +#endif /* CONFIG_SOFTMMU */ + static void init_proc_POWER7 (CPUPPCState *env) { init_proc_book3s_64(env, BOOK3S_CPU_POWER7); @@ -8167,6 +8197,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; + pcc->sps = &POWER7_POWER8_sps; #endif pcc->excp_model = POWERPC_EXCP_POWER7; pcc->bus_model = PPC_FLAGS_INPUT_POWER7; @@ -8247,6 +8278,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; + pcc->sps = &POWER7_POWER8_sps; #endif pcc->excp_model = POWERPC_EXCP_POWER7; pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
Now that the TCG and spapr code has been extended to allow (semi-) arbitrary page encodings in the CPU's 'sps' table, we can add the many page sizes supported by real POWER7 and POWER8 hardware that we previously didn't support in TCG. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> --- target-ppc/mmu-hash64.h | 2 ++ target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+)