| Message ID | 1454384899-7270-1-git-send-email-wxt@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Caesar, Xing, Am Dienstag, 2. Februar 2016, 11:48:19 schrieb Caesar Wang: > From: zhengxing <zhengxing@rock-chips.com> > > In the emac driver, we need to refer HCLK_MAC since there are > only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clock are under the > GPLL, and it is unable to provide the accurate rate for mac_ref which > need to 50MHz probability, we should let it under the DPLL and are > able to set the freq which integer multiples of 50MHz, so we add these > emac node for reference. > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > Signed-off-by: Caesar Wang <wxt@rock-chips.com> [...] > --- a/drivers/clk/rockchip/clk-rk3036.c > +++ b/drivers/clk/rockchip/clk-rk3036.c > @@ -343,8 +343,11 @@ static struct rockchip_clk_branch > rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, > 2, 5, DFLAGS, > RK2928_CLKGATE_CON(10), 5, GFLAGS), > > - COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, > - RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), > + MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0, > + RK2928_CLKSEL_CON(21), 0, 2, MFLAGS), > + DIV(0, "mac_pll_src", "mac_pll_pre", 0, > + RK2928_CLKSEL_CON(21), 9, 5, DFLAGS), > + CLK_SET_RATE_NO_REPARENT should do the trick as well. And the whole hclk + clkid part should be separate patches. I took the liberty of splitting them already in [0] to see if I could get the emac running on my kylin board. Probing emac + phy does suceed, but there is no link-detection. Building your kylin-develop4.4 branch [1] results in the same (aka no transmission). Only with the original uboot + 4.1-based kernel that was already on the device did I manage to get a network connection. Is there some additional setup missing somewhere? Heiko [0] https://github.com/mmind/linux-rockchip/commits/tmp/rk3036-emac The 3 additional patches are not strictly necessary there. [1] https://github.com/rockchip-linux/kernel/tree/kylin-develop4.4
Heiko, ? 2016?02?21? 10:26, Heiko Stuebner ??: > Hi Caesar, Xing, > > Am Dienstag, 2. Februar 2016, 11:48:19 schrieb Caesar Wang: >> From: zhengxing <zhengxing@rock-chips.com> >> >> In the emac driver, we need to refer HCLK_MAC since there are >> only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clock are under the >> GPLL, and it is unable to provide the accurate rate for mac_ref which >> need to 50MHz probability, we should let it under the DPLL and are >> able to set the freq which integer multiples of 50MHz, so we add these >> emac node for reference. >> >> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> >> Signed-off-by: Caesar Wang <wxt@rock-chips.com> > [...] > >> --- a/drivers/clk/rockchip/clk-rk3036.c >> +++ b/drivers/clk/rockchip/clk-rk3036.c >> @@ -343,8 +343,11 @@ static struct rockchip_clk_branch >> rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, >> 2, 5, DFLAGS, >> RK2928_CLKGATE_CON(10), 5, GFLAGS), >> >> - COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, >> - RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), >> + MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0, >> + RK2928_CLKSEL_CON(21), 0, 2, MFLAGS), >> + DIV(0, "mac_pll_src", "mac_pll_pre", 0, >> + RK2928_CLKSEL_CON(21), 9, 5, DFLAGS), >> + > CLK_SET_RATE_NO_REPARENT should do the trick as well. > > And the whole hclk + clkid part should be separate patches. I took the > liberty of splitting them already in [0] to see if I could get the emac > running on my kylin board. > > Probing emac + phy does suceed, but there is no link-detection. > Building your kylin-develop4.4 branch [1] results in the same (aka no > transmission). > > Only with the original uboot + 4.1-based kernel that was already on the > device did I manage to get a network connection. I guess you need apply the uboot patch[0]. patch[0]: http://lists.denx.de/pipermail/u-boot/2016-February/245814.html or get the uboot from rockchip github: https://github.com/rockchip-linux/u-boot/commits/rk3036 > > Is there some additional setup missing somewhere? > > > Heiko > > [0] https://github.com/mmind/linux-rockchip/commits/tmp/rk3036-emac > The 3 additional patches are not strictly necessary there. > > [1] https://github.com/rockchip-linux/kernel/tree/kylin-develop4.4 The lastest kylin-develop.4.4.y from my github: https://github.com/Caesar-github/rockchip/tree/kylin/develop-4.4.y > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip
Am Sonntag, 21. Februar 2016, 10:45:11 schrieb Caesar Wang: > Heiko, > > ? 2016?02?21? 10:26, Heiko Stuebner ??: > > Hi Caesar, Xing, > > > > Am Dienstag, 2. Februar 2016, 11:48:19 schrieb Caesar Wang: > >> From: zhengxing <zhengxing@rock-chips.com> > >> > >> In the emac driver, we need to refer HCLK_MAC since there are > >> only 3PLLs (APLL/GPLL/DPLL) on the rk3036, most clock are under the > >> GPLL, and it is unable to provide the accurate rate for mac_ref which > >> need to 50MHz probability, we should let it under the DPLL and are > >> able to set the freq which integer multiples of 50MHz, so we add these > >> emac node for reference. > >> > >> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> > >> Signed-off-by: Caesar Wang <wxt@rock-chips.com> > > > > [...] > > > >> --- a/drivers/clk/rockchip/clk-rk3036.c > >> +++ b/drivers/clk/rockchip/clk-rk3036.c > >> @@ -343,8 +343,11 @@ static struct rockchip_clk_branch > >> rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(16), 0, 2, > >> MFLAGS, > >> 2, 5, DFLAGS, > >> > >> RK2928_CLKGATE_CON(10), 5, GFLAGS), > >> > >> - COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, > >> - RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), > >> + MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0, > >> + RK2928_CLKSEL_CON(21), 0, 2, MFLAGS), > >> + DIV(0, "mac_pll_src", "mac_pll_pre", 0, > >> + RK2928_CLKSEL_CON(21), 9, 5, DFLAGS), > >> + > > > > CLK_SET_RATE_NO_REPARENT should do the trick as well. > > > > And the whole hclk + clkid part should be separate patches. I took the > > liberty of splitting them already in [0] to see if I could get the emac > > running on my kylin board. > > > > Probing emac + phy does suceed, but there is no link-detection. > > Building your kylin-develop4.4 branch [1] results in the same (aka no > > transmission). > > > > Only with the original uboot + 4.1-based kernel that was already on the > > device did I manage to get a network connection. > > I guess you need apply the uboot patch[0]. > > patch[0]: > http://lists.denx.de/pipermail/u-boot/2016-February/245814.html > > or get the uboot from rockchip github: > https://github.com/rockchip-linux/u-boot/commits/rk3036 I have a uboot with the ddr-freq change already, and the clocks look like expected (both on the android system as well as on my mainline kernel with the adapted clock change): pll_dpll 1 1 400000000 0 0 dpll 1 1 400000000 0 0 mac_pll_src 1 1 50000000 0 0 mac_clk_ref 3 3 50000000 0 0 mac_clk 1 1 25000000 0 0 The probing itself also seems to work like a charm: [ 3.064437] rockchip_emac 10200000.ethernet: ARC EMAC detected with id: 0x7fd02 [ 3.072123] rockchip_emac 10200000.ethernet: IRQ is 29 [ 3.090055] rockchip_emac 10200000.ethernet: MAC address is now a2:d6:55:be:be:ad [ 3.100732] libphy: Synopsys MII Bus: probed [ 3.202432] rockchip_emac 10200000.ethernet: connected to RTL8201F Ethernet phy with id 0x1cc816 (same with the real generic phy) Digging a bit into the phy status it looks like it never detects the link, so my current guess is that I have some sort of clock issue that isn't shown in the general clock summary, as the phy should only need the mac clock to do the link negotiation. I'll dig some more. Heiko > > Is there some additional setup missing somewhere? > > > > > > Heiko > > > > [0] https://github.com/mmind/linux-rockchip/commits/tmp/rk3036-emac > > The 3 additional patches are not strictly necessary there. > > > > [1] https://github.com/rockchip-linux/kernel/tree/kylin-develop4.4 > > The lastest kylin-develop.4.4.y from my github: > https://github.com/Caesar-github/rockchip/tree/kylin/develop-4.4.y > > > _______________________________________________ > > Linux-rockchip mailing list > > Linux-rockchip@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-rockchip
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index be71a41..701f702 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -343,8 +343,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, RK2928_CLKGATE_CON(10), 5, GFLAGS), - COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, - RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS), + MUX(SCLK_MACPLL, "mac_pll_pre", mux_pll_src_3plls_p, 0, + RK2928_CLKSEL_CON(21), 0, 2, MFLAGS), + DIV(0, "mac_pll_src", "mac_pll_pre", 0, + RK2928_CLKSEL_CON(21), 9, 5, DFLAGS), + MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), @@ -404,7 +407,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), - GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS), + GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), /* pclk_peri gates */ GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index ebc7a7b..de44109 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -54,6 +54,7 @@ #define SCLK_PVTM_VIDEO 125 #define SCLK_MAC 151 #define SCLK_MACREF 152 +#define SCLK_MACPLL 153 #define SCLK_SFC 160 /* aclk gates */ @@ -92,6 +93,7 @@ #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 +#define HCLK_MAC 460 #define HCLK_I2S 462 #define HCLK_LCDC 465 #define HCLK_ROM 467