From patchwork Tue Feb 2 11:39:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Murzin X-Patchwork-Id: 8189261 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F3411BEEE5 for ; Tue, 2 Feb 2016 11:42:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C099B202E6 for ; Tue, 2 Feb 2016 11:42:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9134620295 for ; Tue, 2 Feb 2016 11:42:53 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQZKo-0005yT-OS; Tue, 02 Feb 2016 11:41:26 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aQZKD-0005cl-5S for linux-arm-kernel@lists.infradead.org; Tue, 02 Feb 2016 11:40:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0D0DB5EA; Tue, 2 Feb 2016 03:39:46 -0800 (PST) Received: from login1.euhpc.arm.com (login1.euhpc.arm.com [10.6.26.143]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 108273F4FF; Tue, 2 Feb 2016 03:40:26 -0800 (PST) From: Vladimir Murzin To: arnd@arndb.de, linux@arm.linux.org.uk, gregkh@linuxfoundation.org, daniel.lezcano@linaro.org, tglx@linutronix.de, u.kleine-koenig@pengutronix.de Subject: [PATCH v2 02/10] clockevents/drivers: add MPS2 Timer driver Date: Tue, 2 Feb 2016 11:39:51 +0000 Message-Id: <1454413199-26573-3-git-send-email-vladimir.murzin@arm.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1454413199-26573-1-git-send-email-vladimir.murzin@arm.com> References: <1454413199-26573-1-git-send-email-vladimir.murzin@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160202_034049_373466_029810A0 X-CRM114-Status: GOOD ( 15.46 ) X-Spam-Score: -7.4 (-------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-api@vger.kernel.org, linux-kernel@vger.kernel.org, andy.shevchenko@gmail.com, robh+dt@kernel.org, linux-serial@vger.kernel.org, galak@codeaurora.org, jslaby@suse.cz, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MPS2 platform has simple 32 bits general purpose countdown timers. The driver uses the first detected timer as a clocksource and the rest of the timers as a clockevent Signed-off-by: Vladimir Murzin Acked-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 6 + drivers/clocksource/Makefile | 1 + drivers/clocksource/mps2-timer.c | 276 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 283 insertions(+) create mode 100644 drivers/clocksource/mps2-timer.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 33db740..7ce3892 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -185,6 +185,12 @@ config CLKSRC_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) select CLKSRC_MMIO +config CLKSRC_MPS2 + bool "Clocksource for MPS2 SoCs" if COMPILE_TEST + depends on GENERIC_SCHED_CLOCK + select CLKSRC_MMIO + select CLKSRC_OF + config ARM_ARCH_TIMER bool select CLKSRC_OF if OF diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dc2b899..b0a3c96 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o +obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o diff --git a/drivers/clocksource/mps2-timer.c b/drivers/clocksource/mps2-timer.c new file mode 100644 index 0000000..0f529e9f --- /dev/null +++ b/drivers/clocksource/mps2-timer.c @@ -0,0 +1,276 @@ +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Vladimir Murzin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER_CTRL 0x0 +#define TIMER_CTRL_ENABLE BIT(0) +#define TIMER_CTRL_IE BIT(3) + +#define TIMER_VALUE 0x4 +#define TIMER_RELOAD 0x8 +#define TIMER_INT 0xc + +struct clockevent_mps2 { + void __iomem *reg; + u32 clock_count_per_tick; + struct clock_event_device clkevt; +}; + +static void __iomem *sched_clock_base; + +static u64 notrace mps2_sched_read(void) +{ + return ~readl_relaxed(sched_clock_base + TIMER_VALUE); +} + +static inline struct clockevent_mps2 *to_mps2_clkevt(struct clock_event_device *c) +{ + return container_of(c, struct clockevent_mps2, clkevt); +} + +static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset) +{ + writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); +} + +static int mps2_timer_shutdown(struct clock_event_device *ce) +{ + clockevent_mps2_writel(0, ce, TIMER_RELOAD); + clockevent_mps2_writel(0, ce, TIMER_CTRL); + + return 0; +} + +static int mps2_timer_set_next_event(unsigned long next, struct clock_event_device *ce) +{ + clockevent_mps2_writel(next, ce, TIMER_VALUE); + clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); + + return 0; +} + +static int mps2_timer_set_periodic(struct clock_event_device *ce) +{ + u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; + + clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_RELOAD); + clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_VALUE); + clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL); + + return 0; +} + +static irqreturn_t mps2_timer_interrupt(int irq, void *dev_id) +{ + struct clockevent_mps2 *ce = dev_id; + u32 status = readl_relaxed(ce->reg + TIMER_INT); + + if (!status) { + pr_warn("spurious interrupt\n"); + return IRQ_NONE; + } + + writel_relaxed(1, ce->reg + TIMER_INT); + + ce->clkevt.event_handler(&ce->clkevt); + + return IRQ_HANDLED; +} + +static int __init mps2_clockevent_init(struct device_node *np) +{ + void __iomem *base; + struct clk *clk; + struct clockevent_mps2 *ce; + u32 rate; + int irq, ret; + const char *name = "mps2-clkevt"; + + ret = of_property_read_u32(np, "clock-frequency", &rate); + if (ret) { + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + pr_err("failed to get clock for clockevent: %d\n", ret); + goto err_clk_get; + } + + ret = clk_prepare_enable(clk); + if (ret) { + pr_err("failed to enable clock for clockevent: %d\n", ret); + clk_put(clk); + goto err_clk_enable; + } + + rate = clk_get_rate(clk); + } + + base = of_iomap(np, 0); + if (!base) { + ret = -EADDRNOTAVAIL; + pr_err("failed to map register for clockevent: %d\n", ret); + goto err_iomap; + } + + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + ret = -ENOENT; + pr_err("failed to get irq for clockevent: %d\n", ret); + goto err_get_irq; + } + + ce = kzalloc(sizeof(struct clockevent_mps2), GFP_KERNEL); + if (!ce) { + ret = -ENOMEM; + goto err_ce_alloc; + } + + ce->reg = base; + ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ); + ce->clkevt.irq = irq; + ce->clkevt.name = name; + ce->clkevt.rating = 200; + ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + ce->clkevt.cpumask = cpu_possible_mask; + ce->clkevt.set_state_shutdown = mps2_timer_shutdown, + ce->clkevt.set_state_periodic = mps2_timer_set_periodic, + ce->clkevt.set_state_oneshot = mps2_timer_shutdown, + ce->clkevt.set_next_event = mps2_timer_set_next_event; + + /* Ensure timer is disabled */ + writel_relaxed(0, base + TIMER_CTRL); + + ret = request_irq(irq, mps2_timer_interrupt, IRQF_TIMER, name, ce); + if (ret) { + pr_err("failed to request irq: %d\n", ret); + goto err_ia_alloc; + } + + clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff); + + return 0; + +err_ia_alloc: + kfree(ce); +err_ce_alloc: +err_get_irq: + iounmap(base); +err_iomap: + clk_disable_unprepare(clk); +err_clk_enable: + clk_put(clk); +err_clk_get: + return ret; +} + +static int __init mps2_clocksource_init(struct device_node *np) +{ + void __iomem *base; + struct clk *clk; + u32 rate; + int ret; + const char *name = "mps2-clksrc"; + + ret = of_property_read_u32(np, "clock-frequency", &rate); + if (ret) { + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + pr_err("failed to get clock for clocksource: %d\n", ret); + goto err_clk_get; + } + + ret = clk_prepare_enable(clk); + if (ret) { + pr_err("failed to enable clock for clocksource: %d\n", ret); + clk_put(clk); + goto err_clk_enable; + } + + rate = clk_get_rate(clk); + } + + base = of_iomap(np, 0); + if (!base) { + ret = -EADDRNOTAVAIL; + pr_err("failed to map register for clocksource: %d\n", ret); + goto err_iomap; + } + + /* Ensure timer is disabled */ + writel_relaxed(0, base + TIMER_CTRL); + + /* ... and set it up as free-running clocksource */ + writel_relaxed(0xffffffff, base + TIMER_VALUE); + writel_relaxed(0xffffffff, base + TIMER_RELOAD); + + writel_relaxed(TIMER_CTRL_ENABLE, base + TIMER_CTRL); + + ret = clocksource_mmio_init(base + TIMER_VALUE, name, + rate, 200, 32, + clocksource_mmio_readl_down); + if (ret) { + pr_err("failed to init clocksource: %d\n", ret); + goto err_clocksource_init; + } + + sched_clock_base = base; + sched_clock_register(mps2_sched_read, 32, rate); + + return 0; + +err_clocksource_init: + iounmap(base); +err_iomap: + clk_disable_unprepare(clk); +err_clk_enable: + clk_put(clk); +err_clk_get: + return ret; +} + +static void __init mps2_timer_init(struct device_node *np) +{ + static int has_clocksource, has_clockevent; + int ret; + + if (!has_clocksource) { + ret = mps2_clocksource_init(np); + if (!ret) { + has_clocksource = 1; + return; + } + } + + if (!has_clockevent) { + ret = mps2_clockevent_init(np); + if (!ret) { + has_clockevent = 1; + return; + } + } +} + +CLOCKSOURCE_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init);