From patchwork Wed Feb 3 11:16:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak M X-Patchwork-Id: 8197941 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 384BB9F38B for ; Wed, 3 Feb 2016 05:42:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0B93120221 for ; Wed, 3 Feb 2016 05:42:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8535420220 for ; Wed, 3 Feb 2016 05:42:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B62AA6E660; Tue, 2 Feb 2016 21:42:23 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTP id D62156E660 for ; Tue, 2 Feb 2016 21:42:21 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP; 02 Feb 2016 21:42:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,388,1449561600"; d="scan'208";a="739605381" Received: from mdeepakubuntudesk01-desktop.iind.intel.com ([10.223.26.119]) by orsmga003.jf.intel.com with ESMTP; 02 Feb 2016 21:42:20 -0800 From: Deepak M To: intel-gfx@lists.freedesktop.org Date: Wed, 3 Feb 2016 16:46:45 +0530 Message-Id: <1454498205-5983-1-git-send-email-m.deepak@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <201602031358.39xFct71%fengguang.wu@intel.com> References: <201602031358.39xFct71%fengguang.wu@intel.com> Cc: Deepak M Subject: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_03_06, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The MIPI clock calculations for the addtional clock are revised from B0 stepping onwards, the bit definitions have changed compared to old stepping. v2: Fixing compilation warning. Signed-off-by: Deepak M --- drivers/gpu/drm/i915/i915_reg.h | 104 +++++++++++++++++------------------ drivers/gpu/drm/i915/intel_dsi_pll.c | 64 ++++++++++++++------- 2 files changed, 95 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c0bd691..2568f35 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7638,6 +7638,57 @@ enum skl_disp_power_wells { /* MIPI DSI registers */ +#define BXT_MIPI1_RX_LOWER_SHIFT 16 +#define BXT_MIPI2_RX_LOWER_SHIFT 0 +#define BXT_MIPI_RX_LOWER_SHIFT(port) \ + _MIPI_PORT(port, BXT_MIPI1_RX_LOWER_SHIFT, \ + BXT_MIPI2_RX_LOWER_SHIFT) +#define BXT_MIPI1_RX_LOWER_DIVIDER_MASK (3 << 16) +#define BXT_MIPI2_RX_LOWER_DIVIDER_MASK (3 << 0) +#define BXT_MIPI_RX_LOWER_DIVIDER_MASK(port) \ + (3 << BXT_MIPI_RX_LOWER_SHIFT(port)) +#define BXT_MIPI_RX_LOWER_DIVIDER(port, val) \ + ((val & 3) << BXT_MIPI_RX_LOWER_SHIFT(port)) + +#define BXT_MIPI1_8X_BY3_SHIFT 19 +#define BXT_MIPI2_8X_BY3_SHIFT 3 +#define BXT_MIPI_8X_BY3_SHIFT(port) \ + _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ + BXT_MIPI2_8X_BY3_SHIFT) +#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) +#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) +#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ + (3 << BXT_MIPI_8X_BY3_SHIFT(port)) +#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ + ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) + +#define BXT_MIPI1_RX_UPPER_SHIFT 21 +#define BXT_MIPI2_RX_UPPER_SHIFT 5 +#define BXT_MIPI_RX_UPPER_SHIFT(port) \ + _MIPI_PORT(port, BXT_MIPI1_RX_UPPER_SHIFT, \ + BXT_MIPI2_RX_UPPER_SHIFT) +#define BXT_MIPI1_RX_UPPER_DIVIDER_MASK (3 << 21) +#define BXT_MIPI2_RX_UPPER_DIVIDER_MASK (3 << 5) +#define BXT_MIPI_RX_UPPER_DIVIDER_MASK(port) \ + (3 << BXT_MIPI_RX_UPPER_SHIFT(port)) +#define BXT_MIPI_RX_UPPER_DIVIDER(port, val) \ + ((val & 3) << BXT_MIPI_RX_UPPER_SHIFT(port)) + +#define BXT_MIPI1_TX_SHIFT 26 +#define BXT_MIPI2_TX_SHIFT 10 +#define BXT_MIPI_TX_SHIFT(port) \ + _MIPI_PORT(port, BXT_MIPI1_TX_SHIFT, \ + BXT_MIPI2_TX_SHIFT) +#define BXT_MIPI1_TX_DIVIDER_MASK (0x3F << 26) +#define BXT_MIPI2_TX_DIVIDER_MASK (0x3F << 10) +#define BXT_MIPI_TX_DIVIDER_MASK(port) \ + (0x3F << BXT_MIPI_TX_SHIFT(port)) +#define BXT_MIPI_TX_DIVIDER(port, val) \ + ((val & 0x3F) << BXT_MIPI_TX_SHIFT(port)) + +#define RX_DIVIDER_BIT_1_2 0x3 +#define RX_DIVIDER_BIT_3_4 0xC + #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) @@ -7650,59 +7701,6 @@ enum skl_disp_power_wells { #define BXT_MIPI_DIV_SHIFT(port) \ _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ BXT_MIPI2_DIV_SHIFT) -/* Var clock divider to generate TX source. Result must be < 39.5 M */ -#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26) -#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10) -#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \ - _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \ - BXT_MIPI2_ESCLK_VAR_DIV_MASK) - -#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \ - (val << BXT_MIPI_DIV_SHIFT(port)) -/* TX control divider to select actual TX clock output from (8x/var) */ -#define BXT_MIPI1_TX_ESCLK_SHIFT 21 -#define BXT_MIPI2_TX_ESCLK_SHIFT 5 -#define BXT_MIPI_TX_ESCLK_SHIFT(port) \ - _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ - BXT_MIPI2_TX_ESCLK_SHIFT) -#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21) -#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5) -#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ - _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ - BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) -#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \ - (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port)) -#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \ - (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port)) -#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \ - (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port)) -/* RX control divider to select actual RX clock output from 8x*/ -#define BXT_MIPI1_RX_ESCLK_SHIFT 19 -#define BXT_MIPI2_RX_ESCLK_SHIFT 3 -#define BXT_MIPI_RX_ESCLK_SHIFT(port) \ - _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \ - BXT_MIPI2_RX_ESCLK_SHIFT) -#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19) -#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3) -#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \ - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port)) -#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \ - (1 << BXT_MIPI_RX_ESCLK_SHIFT(port)) -#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \ - (2 << BXT_MIPI_RX_ESCLK_SHIFT(port)) -#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \ - (3 << BXT_MIPI_RX_ESCLK_SHIFT(port)) -/* BXT-A WA: Always prog DPHY dividers to 00 */ -#define BXT_MIPI1_DPHY_DIV_SHIFT 16 -#define BXT_MIPI2_DPHY_DIV_SHIFT 0 -#define BXT_MIPI_DPHY_DIV_SHIFT(port) \ - _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \ - BXT_MIPI2_DPHY_DIV_SHIFT) -#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16) -#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0) -#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \ - (3 << BXT_MIPI_DPHY_DIV_SHIFT(port)) - /* BXT MIPI mode configure */ #define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 #define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index bb5e95a..7435115 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -362,35 +362,59 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) /* Program BXT Mipi clocks and dividers */ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) { - u32 tmp; - u32 divider; - u32 dsi_rate; - u32 pll_ratio; struct drm_i915_private *dev_priv = dev->dev_private; + u32 tmp; + u32 dsi_rate = 0; + u32 pll_ratio = 0; + u32 rx_div; + u32 tx_div; + u32 rx_div_upper; + u32 rx_div_lower; + u32 mipi_8by3_divider; /* Clear old configurations */ tmp = I915_READ(BXT_MIPI_CLOCK_CTL); - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); + tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port)); + tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port)); + tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port)); /* Get the current DSI rate(actual) */ pll_ratio = I915_READ(BXT_DSI_PLL_CTL) & - BXT_DSI_PLL_RATIO_MASK; + BXT_DSI_PLL_RATIO_MASK; + + /* To get 8X clock, divide ref_freq * pll ratio by 2 as per bspec */ dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; - /* Max possible output of clock is 39.5 MHz, program value -1 */ - divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1; - tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider); + /* + * tx clock should be <= 20MHz and the div value must be + * subtracted by 1 as per bspec + */ + tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1; + /* + * rx clock should be <= 150MHz and the div value must be + * subtracted by 1 as per bspec + */ + rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1; /* - * Tx escape clock must be as close to 20MHz possible, but should - * not exceed it. Hence select divide by 2 + * rx divider value needs to be updated in the + * two differnt bit fields in the register hence splitting the + * rx divider value accordingly */ - tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port); + rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; + rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2; + + /* As per bpsec program the 8/3X clock divider to the below value */ + if (dev_priv->vbt.dsi.config->is_cmd_mode) + mipi_8by3_divider = 0x2; + else + mipi_8by3_divider = 0x3; - tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port); + tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider); + tmp |= BXT_MIPI_TX_DIVIDER(port, tx_div); + tmp |= BXT_MIPI_RX_LOWER_DIVIDER(port, rx_div_lower); + tmp |= BXT_MIPI_RX_UPPER_DIVIDER(port, rx_div_upper); I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); } @@ -512,10 +536,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) /* Clear old configurations */ tmp = I915_READ(BXT_MIPI_CLOCK_CTL); - tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); - tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); - tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); - tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); + tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); + tmp &= ~(BXT_MIPI_RX_LOWER_DIVIDER_MASK(port)); + tmp &= ~(BXT_MIPI_RX_UPPER_DIVIDER_MASK(port)); + tmp &= ~(BXT_MIPI_TX_DIVIDER_MASK(port)); I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); }