From patchwork Mon Feb 8 16:47:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 8252151 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3A191BEEE5 for ; Mon, 8 Feb 2016 16:49:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E5DF20380 for ; Mon, 8 Feb 2016 16:49:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C4F22203AE for ; Mon, 8 Feb 2016 16:49:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932140AbcBHQtc (ORCPT ); Mon, 8 Feb 2016 11:49:32 -0500 Received: from foss.arm.com ([217.140.101.70]:34387 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755155AbcBHQsO (ORCPT ); Mon, 8 Feb 2016 11:48:14 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BFBE44A7; Mon, 8 Feb 2016 08:47:27 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 38C033F5D0; Mon, 8 Feb 2016 08:48:12 -0800 (PST) From: Julien Grall To: kvmarm@lists.cs.columbia.edu Cc: christoffer.dall@linaro.org, marc.zyngier@arm.com, fu.wei@linaro.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wei@redhat.com, al.stone@linaro.org, Julien Grall , Thomas Gleixner , Jason Cooper Subject: [PATCH 3/5] irqchip/gic-v2: Parse and export virtual GIC information Date: Mon, 8 Feb 2016 16:47:27 +0000 Message-Id: <1454950049-741-4-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1454950049-741-1-git-send-email-julien.grall@arm.com> References: <1454950049-741-1-git-send-email-julien.grall@arm.com> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For now, the firmware tables are parsed 2 times: once in the GIC drivers, the other timer when initializing the vGIC. It means code duplication and make more tedious to add the support for another firmware table (like ACPI). Introduce a new structure and set of helpers to get/set the virtual GIC information. Also fill up the structure for GICv2. Signed-off-by: Julien Grall --- Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier drivers/irqchip/irq-gic-common.c | 13 ++++++ drivers/irqchip/irq-gic-common.h | 3 ++ drivers/irqchip/irq-gic.c | 78 +++++++++++++++++++++++++++++++++- include/linux/irqchip/arm-gic-common.h | 34 +++++++++++++++ 4 files changed, 127 insertions(+), 1 deletion(-) create mode 100644 include/linux/irqchip/arm-gic-common.h diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c index f174ce0..704caf4 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c @@ -21,6 +21,19 @@ #include "irq-gic-common.h" +static const struct gic_kvm_info *gic_kvm_info; + +const struct gic_kvm_info *gic_get_kvm_info(void) +{ + return gic_kvm_info; +} + +void gic_set_kvm_info(const struct gic_kvm_info *info) +{ + WARN(gic_kvm_info != NULL, "gic_kvm_info already set\n"); + gic_kvm_info = info; +} + void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, void *data) { diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h index fff697d..205e5fd 100644 --- a/drivers/irqchip/irq-gic-common.h +++ b/drivers/irqchip/irq-gic-common.h @@ -19,6 +19,7 @@ #include #include +#include struct gic_quirk { const char *desc; @@ -35,4 +36,6 @@ void gic_cpu_config(void __iomem *base, void (*sync_access)(void)); void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, void *data); +void gic_set_kvm_info(const struct gic_kvm_info *info); + #endif /* _IRQ_GIC_COMMON_H */ diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 911758c..d3a09a4 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -102,6 +102,8 @@ static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; +static struct gic_kvm_info gic_v2_kvm_info; + #ifdef CONFIG_GIC_NON_BANKED static void __iomem *gic_get_percpu_base(union gic_base *base) { @@ -1190,6 +1192,44 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base) return true; } +static void __init gic_of_setup_kvm_info(struct device_node *node) +{ + int ret; + struct resource r; + unsigned int irq; + + gic_v2_kvm_info.type = GIC_V2; + + irq = irq_of_parse_and_map(node, 0); + if (!irq) + gic_v2_kvm_info.maint_irq = -1; + else + gic_v2_kvm_info.maint_irq = irq; + + ret = of_address_to_resource(node, 2, &r); + if (!ret) { + gic_v2_kvm_info.vctrl_base = r.start; + gic_v2_kvm_info.vctrl_size = resource_size(&r); + } + + ret = of_address_to_resource(node, 3, &r); + if (!ret) { + if (!PAGE_ALIGNED(r.start)) + pr_warn("GICV physical address 0x%llx not page aligned\n", + (unsigned long long)r.start); + else if (!PAGE_ALIGNED(resource_size(&r))) + pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n", + (unsigned long long)resource_size(&r), + PAGE_SIZE); + else { + gic_v2_kvm_info.vcpu_base = r.start; + gic_v2_kvm_info.vcpu_size = resource_size(&r); + } + } + + gic_set_kvm_info(&gic_v2_kvm_info); +} + int __init gic_of_init(struct device_node *node, struct device_node *parent) { @@ -1219,8 +1259,10 @@ gic_of_init(struct device_node *node, struct device_node *parent) __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, &node->fwnode); - if (!gic_cnt) + if (!gic_cnt) { gic_init_physaddr(node); + gic_of_setup_kvm_info(node); + } if (parent) { irq = irq_of_parse_and_map(node, 0); @@ -1247,6 +1289,32 @@ IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); #ifdef CONFIG_ACPI static phys_addr_t cpu_phy_base __initdata; +static struct +{ + u32 maint_irq; + int maint_irq_mode; + phys_addr_t vctrl_base; + phys_addr_t vcpu_base; +} acpi_data __initdata; + +static void __init gic_acpi_setup_kvm_info(void) +{ + gic_v2_kvm_info.type = GIC_V2; + + gic_v2_kvm_info.maint_irq = acpi_register_gsi(NULL, + acpi_data.maint_irq, + acpi_data.maint_irq_mode, + ACPI_ACTIVE_HIGH); + gic_v2_kvm_info.vctrl_base = acpi_data.vctrl_base; + if (gic_v2_kvm_info.vctrl_base) + gic_v2_kvm_info.vctrl_size = SZ_8K; + + gic_v2_kvm_info.vcpu_base = acpi_data.vcpu_base; + if (gic_v2_kvm_info.vcpu_base) + gic_v2_kvm_info.vcpu_size = SZ_8K; + + gic_set_kvm_info(&gic_v2_kvm_info); +} static int __init gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, @@ -1270,6 +1338,12 @@ gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, return -EINVAL; cpu_phy_base = gic_cpu_base; + acpi_data.maint_irq = processor->vgic_interrupt; + acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? + ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; + acpi_data.vctrl_base = processor->gich_base_address; + acpi_data.vcpu_base = processor->gicv_base_address; + cpu_base_assigned = 1; return 0; } @@ -1357,6 +1431,8 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) gicv2m_init(NULL, gic_data[0].domain); + gic_acpi_setup_kvm_info(); + return 0; } IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, diff --git a/include/linux/irqchip/arm-gic-common.h b/include/linux/irqchip/arm-gic-common.h new file mode 100644 index 0000000..30972b1 --- /dev/null +++ b/include/linux/irqchip/arm-gic-common.h @@ -0,0 +1,34 @@ +/* + * include/linux/irqchip/arm-gic-common.h + * + * Copyright (C) 2016 ARM Limited, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __LINUX_IRQCHIP_ARM_GIC_COMMON_H +#define __LINUX_IRQCHIP_ARM_GIC_COMMON_H + +#include + +enum gic_type { + GIC_V2, +}; + +struct gic_kvm_info { + /* GIC type */ + enum gic_type type; + /* Physical address & size of virtual cpu interface */ + phys_addr_t vcpu_base; + resource_size_t vcpu_size; + /* Interrupt number */ + int maint_irq; + /* Physical address & size of virtual control interface */ + phys_addr_t vctrl_base; + resource_size_t vctrl_size; +}; + +const struct gic_kvm_info *gic_get_kvm_info(void); + +#endif /* __LINUX_IRQCHIP_ARM_GIC_COMMON_H */