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[120.151.179.201]) by smtp.gmail.com with ESMTPSA id 1sm49669183pfm.10.2016.02.09.02.40.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Feb 2016 02:40:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 Feb 2016 21:40:01 +1100 Message-Id: <1455014403-10742-14-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1455014403-10742-1-git-send-email-rth@twiddle.net> References: <1455014403-10742-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::241 Cc: james.hogan@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 13/15] tcg-mips: Use mips64r6 instructions in constant addition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c | 59 ++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 49 insertions(+), 10 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index bda31c2..e0972ba 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -242,12 +242,26 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) case 'I': ct->ct |= TCG_CT_CONST_U16; break; + case 'A': + /* mips r6 can add any constant without needing a temporary. */ + if (use_mips32r6_instructions) { + ct->ct |= TCG_CT_CONST; + break; + } + /* fallthru */ case 'J': ct->ct |= TCG_CT_CONST_S16; break; case 'K': ct->ct |= TCG_CT_CONST_P2M1; break; + case 's': + /* mips r6 can subtract any constant without needing a temporary. */ + if (use_mips32r6_instructions) { + ct->ct |= TCG_CT_CONST; + break; + } + /* fallthru */ case 'N': ct->ct |= TCG_CT_CONST_N16; break; @@ -781,9 +795,10 @@ static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) } static void tcg_out_r6_ofs(TCGContext *s, MIPSInsn opl, MIPSInsn oph, - TCGReg reg0, TCGReg reg1, tcg_target_long ofs) + TCGReg reg0, TCGReg reg1, + tcg_target_long ofs, bool is_mem) { - TCGReg scratch = TCG_TMP0; + TCGReg scratch = is_mem ? TCG_TMP0 : reg0; int16_t lo = ofs; int32_t hi = ofs - lo; @@ -794,9 +809,15 @@ static void tcg_out_r6_ofs(TCGContext *s, MIPSInsn opl, MIPSInsn oph, /* Bits are set in the high 32-bit half. Thus we require th use of DAHI and/or DATI. The R6 manual recommends addition of immediates in order of mid to high (DAUI, DAHI, DATI, OPL) - in order to simplify hardware recognizing these sequences. */ + in order to simplify hardware recognizing these sequences. + Ignore this wrt DADDIU if it will save one instruction. */ - tcg_out_opc_imm(s, OPC_DAUI, scratch, reg1, hi >> 16); + if (hi == 0 && lo != 0 && !is_mem) { + tcg_out_opc_imm(s, OPC_DADDIU, scratch, reg1, lo); + lo = 0; + } else if (hi != 0 || reg1 != scratch) { + tcg_out_opc_imm(s, OPC_DAUI, scratch, reg1, hi >> 16); + } tmp = ofs >> 16 >> 16; if (tmp & 0xffff) { @@ -811,14 +832,16 @@ static void tcg_out_r6_ofs(TCGContext *s, MIPSInsn opl, MIPSInsn oph, tcg_out_opc_imm(s, oph, scratch, reg1, hi >> 16); reg1 = scratch; } - tcg_out_opc_imm(s, opc, reg0, reg1, lo); + if (is_mem || lo != 0 || reg0 != reg1) { + tcg_out_opc_imm(s, opl, reg0, reg1, lo); + } } static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, TCGReg addr, intptr_t ofs) { if (use_mips32r6_instructions) { - tcg_out_r6_ofs(s, opc, ALIAS_PAUI, data, addr, ofs); + tcg_out_r6_ofs(s, opc, ALIAS_PAUI, data, addr, ofs, true); return; } @@ -1852,9 +1875,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_add_i32: + if (use_mips32r6_instructions && c2) { + tcg_out_r6_ofs(s, OPC_ADDIU, OPC_AUI, a0, a1, (int32_t)a2, false); + break; + } i1 = OPC_ADDU, i2 = OPC_ADDIU; goto do_binary; case INDEX_op_add_i64: + if (use_mips32r6_instructions && c2) { + tcg_out_r6_ofs(s, OPC_DADDIU, OPC_DAUI, a0, a1, a2, false); + break; + } i1 = OPC_DADDU, i2 = OPC_DADDIU; goto do_binary; case INDEX_op_or_i32: @@ -1874,9 +1905,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_sub_i32: + if (use_mips32r6_instructions && c2) { + tcg_out_r6_ofs(s, OPC_ADDIU, OPC_AUI, a0, a1, (int32_t)-a2, false); + break; + } i1 = OPC_SUBU, i2 = OPC_ADDIU; goto do_subtract; case INDEX_op_sub_i64: + if (use_mips32r6_instructions && c2) { + tcg_out_r6_ofs(s, OPC_DADDIU, OPC_DAUI, a0, a1, -a2, false); + break; + } i1 = OPC_DSUBU, i2 = OPC_DADDIU; do_subtract: if (c2) { @@ -2208,7 +2247,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_st16_i32, { "rZ", "r" } }, { INDEX_op_st_i32, { "rZ", "r" } }, - { INDEX_op_add_i32, { "r", "rZ", "rJ" } }, + { INDEX_op_add_i32, { "r", "rZ", "rA" } }, { INDEX_op_mul_i32, { "r", "rZ", "rZ" } }, #if !use_mips32r6_instructions { INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } }, @@ -2220,7 +2259,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_divu_i32, { "r", "rZ", "rZ" } }, { INDEX_op_rem_i32, { "r", "rZ", "rZ" } }, { INDEX_op_remu_i32, { "r", "rZ", "rZ" } }, - { INDEX_op_sub_i32, { "r", "rZ", "rN" } }, + { INDEX_op_sub_i32, { "r", "rZ", "rs" } }, { INDEX_op_and_i32, { "r", "rZ", "rIK" } }, { INDEX_op_nor_i32, { "r", "rZ", "rZ" } }, @@ -2270,7 +2309,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_st32_i64, { "rZ", "r" } }, { INDEX_op_st_i64, { "rZ", "r" } }, - { INDEX_op_add_i64, { "r", "rZ", "rJ" } }, + { INDEX_op_add_i64, { "r", "rZ", "rA" } }, { INDEX_op_mul_i64, { "r", "rZ", "rZ" } }, #if !use_mips32r6_instructions { INDEX_op_muls2_i64, { "r", "r", "rZ", "rZ" } }, @@ -2282,7 +2321,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_divu_i64, { "r", "rZ", "rZ" } }, { INDEX_op_rem_i64, { "r", "rZ", "rZ" } }, { INDEX_op_remu_i64, { "r", "rZ", "rZ" } }, - { INDEX_op_sub_i64, { "r", "rZ", "rN" } }, + { INDEX_op_sub_i64, { "r", "rZ", "rs" } }, { INDEX_op_and_i64, { "r", "rZ", "rIK" } }, { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },