From patchwork Mon Feb 22 13:25:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Deepak M X-Patchwork-Id: 8376361 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A7979C0553 for ; Mon, 22 Feb 2016 13:25:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0C7BB203A9 for ; Mon, 22 Feb 2016 13:25:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E05C72034B for ; Mon, 22 Feb 2016 13:25:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 398E26E1AE; Mon, 22 Feb 2016 13:25:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTP id 648A56E1AE for ; Mon, 22 Feb 2016 13:25:43 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP; 22 Feb 2016 05:25:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,484,1449561600"; d="scan'208";a="750916358" Received: from mdeepakubuntudesk01-desktop.iind.intel.com ([10.223.26.119]) by orsmga003.jf.intel.com with ESMTP; 22 Feb 2016 05:25:42 -0800 From: Deepak M To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Feb 2016 18:55:35 +0530 Message-Id: <1456147535-19730-1-git-send-email-m.deepak@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <87povsx256.fsf@intel.com> References: <87povsx256.fsf@intel.com> MIME-Version: 1.0 Cc: Jani Nikula , Deepak M Subject: [Intel-gfx] [GPIO PATCH 1/2] drm/i915: GPIO for CHT generic MIPI X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yogesh Mohan Marimuthu The GPIO configuration and register offsets are different from baytrail for cherrytrail. Port the gpio programming accordingly for cherrytrail in this patch. v2: Removing the duplication of parsing Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: Yogesh Mohan Marimuthu Signed-off-by: Deepak M --- drivers/gpu/drm/i915/i915_reg.h | 20 ++++++ drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 107 ++++++++++++++++++++++------- 2 files changed, 102 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 606dc71..fc57477 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -615,6 +615,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define IOSF_PORT_NC 0x11 #define IOSF_PORT_DPIO 0x12 #define IOSF_PORT_GPIO_NC 0x13 +#define CHV_IOSF_PORT_GPIO_N 0x13 +#define CHV_IOSF_PORT_GPIO_SE 0x48 +#define CHV_IOSF_PORT_GPIO_SW 0xB2 +#define CHV_IOSF_PORT_GPIO_E 0xA8 +#define CHV_MAX_GPIO_NUM_N 72 +#define CHV_MAX_GPIO_NUM_SE 99 +#define CHV_MAX_GPIO_NUM_SW 197 +#define CHV_MIN_GPIO_NUM_SE 73 +#define CHV_MIN_GPIO_NUM_SW 100 +#define CHV_MIN_GPIO_NUM_E 198 #define IOSF_PORT_CCK 0x14 #define IOSF_PORT_DPIO_2 0x1a #define IOSF_PORT_FLISDSI 0x1b @@ -630,6 +640,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VLV_GPIO_CFG 0x2000CC00 #define VLV_GPIO_INPUT_DIS 0x04 +#define CHV_PAD_FMLY_BASE 0x4400 +#define CHV_PAD_FMLY_SIZE 0x400 +#define CHV_PAD_CFG_0_1_REG_SIZE 0x8 +#define CHV_PAD_CFG_REG_SIZE 0x4 +#define CHV_VBT_MAX_PINS_PER_FMLY 15 + +#define CHV_GPIO_CFG_UNLOCK 0x00000000 +#define CHV_GPIO_CFG_HIZ 0x00008100 +#define CHV_GPIO_CFG_TX_STATE_SHIFT 1 + /* See configdb bunit SB addr map */ #define BUNIT_REG_BISOC 0x11 diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c index 794bd1f..4849515 100644 --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c @@ -685,34 +685,13 @@ static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) return data; } -static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) +void vlv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action) { - u8 gpio, action; + struct drm_device *dev = intel_dsi->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; u16 function, pad; u32 val; u8 port; - struct drm_device *dev = intel_dsi->base.base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - - DRM_DEBUG_DRIVER("MIPI: executing gpio element\n"); - - if (dev_priv->vbt.dsi.seq_version >= 3) - data++; - - gpio = *data++; - - /* pull up/down */ - action = *data++ & 1; - - if (gpio >= ARRAY_SIZE(gtable)) { - DRM_DEBUG_KMS("unknown gpio %u\n", gpio); - goto out; - } - - if (!IS_VALLEYVIEW(dev_priv)) { - DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); - goto out; - } if (dev_priv->vbt.dsi.seq_version >= 3) { if (gpio <= IOSF_MAX_GPIO_NUM_NC) { @@ -728,7 +707,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) port = IOSF_PORT_GPIO_SUS; } else { DRM_ERROR("GPIO number is not present in the table\n"); - goto out; + return; } } else { port = IOSF_PORT_GPIO_NC; @@ -750,11 +729,89 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) /* pull up/down */ vlv_iosf_sb_write(dev_priv, port, pad, val); mutex_unlock(&dev_priv->sb_lock); +} + +void chv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action) +{ + struct drm_device *dev = intel_dsi->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u16 function, pad; + u16 family_num; + u8 block; + + if (dev_priv->vbt.dsi.seq_version >= 3) { + if (gpio <= CHV_MAX_GPIO_NUM_N) { + block = CHV_IOSF_PORT_GPIO_N; + DRM_DEBUG_DRIVER("GPIO is in the north Block\n"); + } else if (gpio <= CHV_MAX_GPIO_NUM_SE) { + block = CHV_IOSF_PORT_GPIO_SE; + gpio = gpio - CHV_MIN_GPIO_NUM_SE; + DRM_DEBUG_DRIVER("GPIO is in the south east Block\n"); + } else if (gpio <= CHV_MAX_GPIO_NUM_SW) { + block = CHV_IOSF_PORT_GPIO_SW; + gpio = gpio - CHV_MIN_GPIO_NUM_SW; + DRM_DEBUG_DRIVER("GPIO is in the south west Block\n"); + } else { + block = CHV_IOSF_PORT_GPIO_E; + gpio = gpio - CHV_MIN_GPIO_NUM_E; + DRM_DEBUG_DRIVER("GPIO is in the east Block\n"); + } + } else + block = IOSF_PORT_GPIO_NC; + + family_num = gpio / CHV_VBT_MAX_PINS_PER_FMLY; + gpio = gpio - (family_num * CHV_VBT_MAX_PINS_PER_FMLY); + pad = CHV_PAD_FMLY_BASE + (family_num * CHV_PAD_FMLY_SIZE) + + (((u16)gpio) * CHV_PAD_CFG_0_1_REG_SIZE); + function = pad + CHV_PAD_CFG_REG_SIZE; + + mutex_lock(&dev_priv->sb_lock); + vlv_iosf_sb_write(dev_priv, block, function, + CHV_GPIO_CFG_UNLOCK); + vlv_iosf_sb_write(dev_priv, block, pad, CHV_GPIO_CFG_HIZ | + (action << CHV_GPIO_CFG_TX_STATE_SHIFT)); + mutex_unlock(&dev_priv->sb_lock); + +} + +static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) +{ + u8 gpio, action; + struct drm_device *dev = intel_dsi->base.base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + DRM_DEBUG_DRIVER("MIPI: executing gpio element\n"); + + if (dev_priv->vbt.dsi.seq_version >= 3) + data++; + + gpio = *data++; + + /* pull up/down */ + action = *data++ & 1; + + if (gpio >= ARRAY_SIZE(gtable)) { + DRM_DEBUG_KMS("unknown gpio %u\n", gpio); + goto out; + } + + if (!IS_VALLEYVIEW(dev_priv)) { + DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); + goto out; + } + + if (IS_VALLEYVIEW(dev)) + vlv_program_gpio(intel_dsi, gpio, action); + else if (IS_CHERRYVIEW(dev)) + chv_program_gpio(intel_dsi, gpio, action); + else + DRM_ERROR("GPIO programming missing for this platform.\n"); out: return data; } + static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data) { return data + *(data + 6) + 7;