From patchwork Wed Feb 24 01:18:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 8397731 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 26553C0553 for ; Wed, 24 Feb 2016 01:20:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3982520295 for ; Wed, 24 Feb 2016 01:20:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 52CEF20251 for ; Wed, 24 Feb 2016 01:20:23 +0000 (UTC) Received: from localhost ([::1]:60905 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYO7q-0006lX-Mq for patchwork-qemu-devel@patchwork.kernel.org; Tue, 23 Feb 2016 20:20:22 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53048) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYO6H-0004na-1j for qemu-devel@nongnu.org; Tue, 23 Feb 2016 20:18:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aYO6E-0002aB-UH for qemu-devel@nongnu.org; Tue, 23 Feb 2016 20:18:44 -0500 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:34739) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYO6E-0002Zz-5d for qemu-devel@nongnu.org; Tue, 23 Feb 2016 20:18:42 -0500 Received: by mail-pf0-x236.google.com with SMTP id x65so2537289pfb.1 for ; Tue, 23 Feb 2016 17:18:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=W1i91zANvoFTe2P1a9Bq8g8WXmjNPOsa+dwM87Gnpkk=; b=mYqy7tF9WhqmVoUd6G5psW1lXWakVm85e2vvuBQ2+/r92PkyUKBpaDRwHYXugeQkTR sU+/kueEv2O8hWPJW53IB3M+VkWg0rTVIpLFhaX4HKnTs4B1pt7IIeq1Lm0m4TDfPonq 8FqPZW6St6BAaY14FcjdJ6JQIzILEU2dXDIOegGdFqxcdJ4heN1VN+QOF+joYfEF+7OH SBXv87LO6aPlyCI4gCylCJTOdQqi4a4/7RjiekkyIiYejaLp81QBVRJRk60lCenG5uyS UT9SY/rveJjR5pksw7VEBNX+ZN5NjK5NHRr7T3P6bwk95Zxy1wHVqKhSnReWJidFllfd B2CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=W1i91zANvoFTe2P1a9Bq8g8WXmjNPOsa+dwM87Gnpkk=; b=keBJenlofrKhwhwtL2bM7KobnGa36fqlUUw197XC7LtqAs9iVoYTVBeFsmGel27led AzlHbhPUwh8WrJHfBm8+7Y++pM5tSElQCxWS0QScn0fV3eDmbk4JzH7Z1n60RTuChAqf qSqjw+Jl/PbUkpb9yV5d4Iceryb+7JxiEihpyLzz09QFGWvy/xerJUOnRNJpZVpgb3I7 DkL5hCAM28+IRI8z3IYzfACyecCl+VlDOwBF8LKpAahGTYJV5jKle5cHRb17gkwHPUfF l3+5U6CI6nFgsf3V+o1x2Q1u1IqUxUq+7BaDe2AhshkJ+RzUs9CEFLWLBDnudVshZwG1 7jhQ== X-Gm-Message-State: AG10YOROBti+QnlxgKiRizIq+tu+OemVBnmzBYsQ8uczlmYYtVRHH3P9os0KvBkWHbXoKg== X-Received: by 10.98.68.194 with SMTP id m63mr50550995pfi.153.1456276721512; Tue, 23 Feb 2016 17:18:41 -0800 (PST) Received: from anchor.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by smtp.gmail.com with ESMTPSA id z5sm361732pas.29.2016.02.23.17.18.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Feb 2016 17:18:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Feb 2016 17:18:36 -0800 Message-Id: <1456276716-28566-4-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1456276716-28566-1-git-send-email-rth@twiddle.net> References: <1456276716-28566-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::236 Cc: agraf@suse.de Subject: [Qemu-devel] [PATCH 3/3] target-ppc: Cleanups to rldinm, rldnm, rldimi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Mirror the cleanups just done to rlwinm, rlwnm and rlwimi. This adds use of deposit to rldimi. Signed-off-by: Richard Henderson --- target-ppc/translate.c | 91 +++++++++++++++++++++++++------------------------- 1 file changed, 46 insertions(+), 45 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b575609..72c1648 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1746,26 +1746,24 @@ static void glue(gen_, name##3)(DisasContext *ctx) \ gen_##name(ctx, 1, 1); \ } -static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, - uint32_t sh) +static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) { - if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { - tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); - } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { - tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); + TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; + TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; + + if (sh != 0 && mb == 0 && me == (63 - sh)) { + tcg_gen_shli_tl(t_ra, t_rs, sh); + } else if (sh != 0 && me == 63 && sh == (64 - mb)) { + tcg_gen_shri_tl(t_ra, t_rs, mb); } else { - TCGv t0 = tcg_temp_new(); - tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); - if (likely(mb == 0 && me == 63)) { - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); - } else { - tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); - } - tcg_temp_free(t0); + tcg_gen_rotli_tl(t_ra, t_rs, sh); + tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); + } + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_Rc0(ctx, t_ra); } - if (unlikely(Rc(ctx->opcode) != 0)) - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); } + /* rldicl - rldicl. */ static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) { @@ -1776,6 +1774,7 @@ static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) gen_rldinm(ctx, mb, 63, sh); } GEN_PPC64_R4(rldicl, 0x1E, 0x00); + /* rldicr - rldicr. */ static inline void gen_rldicr(DisasContext *ctx, int men, int shn) { @@ -1786,6 +1785,7 @@ static inline void gen_rldicr(DisasContext *ctx, int men, int shn) gen_rldinm(ctx, 0, me, sh); } GEN_PPC64_R4(rldicr, 0x1E, 0x02); + /* rldic - rldic. */ static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) { @@ -1797,21 +1797,22 @@ static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) } GEN_PPC64_R4(rldic, 0x1E, 0x04); -static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) +static void gen_rldnm(DisasContext *ctx, int mb, int me) { + TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; + TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; + TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; TCGv t0; t0 = tcg_temp_new(); - tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); - tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - if (unlikely(mb != 0 || me != 63)) { - tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); - } else { - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); - } + tcg_gen_andi_tl(t0, t_rb, 0x3f); + tcg_gen_rotl_tl(t_ra, t_rs, t0); tcg_temp_free(t0); - if (unlikely(Rc(ctx->opcode) != 0)) - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); + + tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_Rc0(ctx, t_ra); + } } /* rldcl - rldcl. */ @@ -1823,6 +1824,7 @@ static inline void gen_rldcl(DisasContext *ctx, int mbn) gen_rldnm(ctx, mb, 63); } GEN_PPC64_R2(rldcl, 0x1E, 0x08); + /* rldcr - rldcr. */ static inline void gen_rldcr(DisasContext *ctx, int men) { @@ -1832,32 +1834,31 @@ static inline void gen_rldcr(DisasContext *ctx, int men) gen_rldnm(ctx, 0, me); } GEN_PPC64_R2(rldcr, 0x1E, 0x09); + /* rldimi - rldimi. */ -static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) +static void gen_rldimi(DisasContext *ctx, int mbn, int shn) { - uint32_t sh, mb, me; + TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; + TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; + uint32_t sh = SH(ctx->opcode) | (shn << 5); + uint32_t mb = MB(ctx->opcode) | (mbn << 5); + uint32_t me = 63 - sh; - sh = SH(ctx->opcode) | (shn << 5); - mb = MB(ctx->opcode) | (mbn << 5); - me = 63 - sh; - if (unlikely(sh == 0 && mb == 0)) { - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); + if (mb <= me) { + tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); } else { - TCGv t0, t1; - target_ulong mask; + target_ulong mask = MASK(mb, me); + TCGv t1 = tcg_temp_new(); - t0 = tcg_temp_new(); - tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); - t1 = tcg_temp_new(); - mask = MASK(mb, me); - tcg_gen_andi_tl(t0, t0, mask); - tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); - tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - tcg_temp_free(t0); + tcg_gen_rotli_tl(t1, t_rs, sh); + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_andi_tl(t_ra, t_ra, ~mask); + tcg_gen_or_tl(t_ra, t_ra, t1); tcg_temp_free(t1); } - if (unlikely(Rc(ctx->opcode) != 0)) - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); + if (unlikely(Rc(ctx->opcode) != 0)) { + gen_set_Rc0(ctx, t_ra); + } } GEN_PPC64_R4(rldimi, 0x1E, 0x06); #endif