[5/5] drm/i915: Bump command parser version for new whitelisted registers
diff mbox

Message ID 1457335830-30923-6-git-send-email-jordan.l.justen@intel.com
State New
Headers show

Commit Message

Jordan Justen March 7, 2016, 7:30 a.m. UTC
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
---
 drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Francisco Jerez March 8, 2016, 10:07 p.m. UTC | #1
Jordan Justen <jordan.l.justen@intel.com> writes:

> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index e1608da..f8381be 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1287,6 +1287,7 @@ int i915_cmd_parser_get_version(void)
>  	 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
>  	 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
>  	 * 5. GPGPU dispatch compute indirect registers.
> +	 * 6. TIMESTAMP register and Haswell CS GPR registers
>  	 */
> -	return 5;
> +	return 6;
>  }
> -- 
> 2.7.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter March 21, 2016, 9:03 a.m. UTC | #2
On Tue, Mar 08, 2016 at 02:07:03PM -0800, Francisco Jerez wrote:
> Jordan Justen <jordan.l.justen@intel.com> writes:
> 
> > Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
> 
> Reviewed-by: Francisco Jerez <currojerez@riseup.net>

Entire series applied to dinq, thanks for patches&review.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index e1608da..f8381be 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -1287,6 +1287,7 @@ int i915_cmd_parser_get_version(void)
> >  	 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
> >  	 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
> >  	 * 5. GPGPU dispatch compute indirect registers.
> > +	 * 6. TIMESTAMP register and Haswell CS GPR registers
> >  	 */
> > -	return 5;
> > +	return 6;
> >  }
> > -- 
> > 2.7.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx




> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index e1608da..f8381be 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1287,6 +1287,7 @@  int i915_cmd_parser_get_version(void)
 	 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
 	 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
 	 * 5. GPGPU dispatch compute indirect registers.
+	 * 6. TIMESTAMP register and Haswell CS GPR registers
 	 */
-	return 5;
+	return 6;
 }