From patchwork Tue Mar 29 01:38:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 8681231 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6020E9F44D for ; Tue, 29 Mar 2016 01:39:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 89175201E4 for ; Tue, 29 Mar 2016 01:39:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A4D5320225 for ; Tue, 29 Mar 2016 01:39:53 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1akibv-0000fW-Aw; Tue, 29 Mar 2016 01:38:23 +0000 Received: from conuserg010.nifty.com ([202.248.44.36] helo=conuserg010-v.nifty.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1akibi-0000Tc-64 for linux-arm-kernel@lists.infradead.org; Tue, 29 Mar 2016 01:38:11 +0000 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg010-v.nifty.com with ESMTP id u2T1baSf005655; Tue, 29 Mar 2016 10:37:37 +0900 X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: arm@kernel.org Subject: [PATCH 1/2] ARM: uniphier: fix up cache ops broadcast of ACTLR Date: Tue, 29 Mar 2016 10:38:23 +0900 Message-Id: <1459215505-18035-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459215505-18035-1-git-send-email-yamada.masahiro@socionext.com> References: <1459215505-18035-1-git-send-email-yamada.masahiro@socionext.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160328_183810_481049_D44CE1FC X-CRM114-Status: GOOD ( 12.13 ) X-Spam-Score: 1.0 (+) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Masahiro Yamada , Russell King , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Boot ROM of the UniPhier ARMv7 SoCs sets ACTLR (Auxiliary Control Register) to different values for different secure states: [1] Set ACTLR to 0x41 for Non-secure boot [2] Set ACTLR to 0x40 for Secure boot [1] is okay, but [2] is a problem. Because of commit 1b3a02eb4523 ("ARMv7: Check whether the SMP/nAMP mode was already enabled"), if bit 6 (SMP bit) is already set, the kernel skips the ACTLR setting. In that case, bit 0 (FW bit) is never set, so cache ops is not broadcasted, causing a cache coherency problem. To solve the problem, this commit sets the bit 0 of ACTLR if the bit 4 has already been set. This change is harmless for [1] because the Boot ROM has already set NSACR (Non-secure Access Control Register) bit 18 (NS_SMP bit) before switching to Non-secure state in order to allow write access to the ACTLR. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/platsmp.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/mach-uniphier/platsmp.c b/arch/arm/mach-uniphier/platsmp.c index db04142..285b684 100644 --- a/arch/arm/mach-uniphier/platsmp.c +++ b/arch/arm/mach-uniphier/platsmp.c @@ -170,6 +170,18 @@ static int __init uniphier_smp_enable_scu(void) return 0; } +static void __init uniphier_smp_fixup_cache_broadcast(void) +{ + u32 tmp; + + asm volatile( + "mrc p15, 0, %0, c1, c0, 1\n" + "tst %0, #(1 << 6)\n" + "orrne %0, #(1 << 0)\n" + "mcr p15, 0, %0, c1, c0, 1\n" + : "=r" (tmp) : : "memory", "cc"); +} + static void __init uniphier_smp_prepare_cpus(unsigned int max_cpus) { static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; @@ -183,6 +195,8 @@ static void __init uniphier_smp_prepare_cpus(unsigned int max_cpus) if (ret) goto err; + uniphier_smp_fixup_cache_broadcast(); + return; err: pr_warn("disabling SMP\n"); @@ -209,9 +223,15 @@ static int __init uniphier_smp_boot_secondary(unsigned int cpu, return 0; } +static void __init uniphier_smp_secondary_init(unsigned int cpu) +{ + uniphier_smp_fixup_cache_broadcast(); +} + static const struct smp_operations uniphier_smp_ops __initconst = { .smp_prepare_cpus = uniphier_smp_prepare_cpus, .smp_boot_secondary = uniphier_smp_boot_secondary, + .smp_secondary_init = uniphier_smp_secondary_init, }; CPU_METHOD_OF_DECLARE(uniphier_smp, "socionext,uniphier-smp", &uniphier_smp_ops);