[1/2] drm/i915: Split execlists hardware status page initialisation from setup
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Message ID 1460472042-1998-1-git-send-email-tvrtko.ursulin@linux.intel.com
State New
Headers show

Commit Message

Tvrtko Ursulin April 12, 2016, 2:40 p.m. UTC
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Split the hardware status page into setup and initialisation,
where setup means setting up the driver state to support the
engine, and initialization means programming the hardware
with the before set up state.

This way the design matches the design of the engine setup/init
code which is split in the same fashion and it enables the
stages to be used in a balanced fashion (engine setup - hws
setup, engine init - hws init).

This will enable the upcoming improvements to slot in without
any kludges on the GPU reset path.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_lrc.c | 50 ++++++++++++++++++++++------------------
 1 file changed, 27 insertions(+), 23 deletions(-)

Comments

Tvrtko Ursulin April 13, 2016, 9:50 a.m. UTC | #1
On 12/04/16 17:54, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Split execlists hardware status page initialisation from setup
> URL   : https://patchwork.freedesktop.org/series/5596/
> State : failure
>
> == Summary ==
>
> Series 5596v1 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/5596/revisions/1/mbox/
>
> Test drv_module_reload_basic:
>                  pass       -> FAIL       (snb-dellxps)

This hasn't been filed so far and it failed once already in CI_DRM_1194?.

Failure are assertions in gem_exec_store after driver reload.

Filed a new BZ: https://bugs.freedesktop.org/show_bug.cgi?id=94914

> Test kms_flip:
>          Subgroup basic-flip-vs-wf_vblank:
>                  pass       -> FAIL       (ivb-t430s)

Old friend https://bugs.freedesktop.org/show_bug.cgi?id=94294

>
> bdw-nuci7        total:203  pass:191  dwarn:0   dfail:0   fail:0   skip:12
> bdw-ultra        total:203  pass:180  dwarn:0   dfail:0   fail:0   skip:23
> bsw-nuc-2        total:202  pass:163  dwarn:0   dfail:0   fail:0   skip:39
> byt-nuc          total:202  pass:164  dwarn:0   dfail:0   fail:0   skip:38
> hsw-brixbox      total:203  pass:179  dwarn:0   dfail:0   fail:0   skip:24
> hsw-gt2          total:203  pass:184  dwarn:0   dfail:0   fail:0   skip:19
> ivb-t430s        total:203  pass:174  dwarn:0   dfail:0   fail:1   skip:28
> skl-i7k-2        total:203  pass:178  dwarn:0   dfail:0   fail:0   skip:25
> skl-nuci5        total:203  pass:192  dwarn:0   dfail:0   fail:0   skip:11
> snb-dellxps      total:203  pass:164  dwarn:0   dfail:0   fail:1   skip:38
> snb-x220t        total:203  pass:165  dwarn:0   dfail:0   fail:1   skip:37
>
> Results at /archive/results/CI_IGT_test/Patchwork_1875/
>
> 42189a46296988a9e16b57dca9e25c227458888b drm-intel-nightly: 2016y-04m-12d-14h-35m-43s UTC integration manifest
> 6d8f2e9 drm/i915: Use new i915_gem_object_pin_map for LRC
> f1b4a09 drm/i915: Split execlists hardware status page initialisation from setup

Merged - thanks for the review.

Regards,

Tvrtko

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e6e69c2f2386..3fd2ae6ce8e7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -229,9 +229,6 @@  enum {
 
 static int intel_lr_context_pin(struct intel_context *ctx,
 				struct intel_engine_cs *engine);
-static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine,
-					   struct drm_i915_gem_object *default_ctx_obj);
-
 
 /**
  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
@@ -1580,14 +1577,22 @@  out:
 	return ret;
 }
 
+static void lrc_init_hws(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->dev->dev_private;
+
+	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
+		   (u32)engine->status_page.gfx_addr);
+	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
+}
+
 static int gen8_init_common_ring(struct intel_engine_cs *engine)
 {
 	struct drm_device *dev = engine->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned int next_context_status_buffer_hw;
 
-	lrc_setup_hardware_status_page(engine,
-				       dev_priv->kernel_context->engine[engine->id].state);
+	lrc_init_hws(engine);
 
 	I915_WRITE_IMR(engine,
 		       ~(engine->irq_enable_mask | engine->irq_keep_mask));
@@ -2087,6 +2092,20 @@  logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
 	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
 }
 
+static void
+lrc_setup_hws(struct intel_engine_cs *engine,
+	      struct drm_i915_gem_object *dctx_obj)
+{
+	struct page *page;
+
+	/* The HWSP is part of the default context object in LRC mode. */
+	engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) +
+				       LRC_PPHWSP_PN * PAGE_SIZE;
+	page = i915_gem_object_get_page(dctx_obj, LRC_PPHWSP_PN);
+	engine->status_page.page_addr = kmap(page);
+	engine->status_page.obj = dctx_obj;
+}
+
 static int
 logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
 {
@@ -2145,6 +2164,9 @@  logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine)
 		goto error;
 	}
 
+	/* And setup the hardware status page. */
+	lrc_setup_hws(engine, dctx->engine[engine->id].state);
+
 	return 0;
 
 error:
@@ -2605,24 +2627,6 @@  uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
 	return ret;
 }
 
-static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine,
-					   struct drm_i915_gem_object *default_ctx_obj)
-{
-	struct drm_i915_private *dev_priv = engine->dev->dev_private;
-	struct page *page;
-
-	/* The HWSP is part of the default context object in LRC mode. */
-	engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj)
-			+ LRC_PPHWSP_PN * PAGE_SIZE;
-	page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN);
-	engine->status_page.page_addr = kmap(page);
-	engine->status_page.obj = default_ctx_obj;
-
-	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
-			(u32)engine->status_page.gfx_addr);
-	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
-}
-
 /**
  * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context
  * @ctx: LR context to create.