@@ -828,7 +828,7 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
&ddev->mode_config.crtc_list, head) {
amdgpu_crtc = to_amdgpu_crtc(crtc);
if (crtc->enabled) {
- info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
+ info->active_display_mask |= (1 << amdgpu_crtc->crtc_object_id.id);
info->display_count++;
}
if (mode_info != NULL &&
@@ -140,7 +140,7 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
- amdgpuCrtc->crtc_id, amdgpuCrtc, work);
+ amdgpuCrtc->crtc_object_id.id, amdgpuCrtc, work);
}
@@ -196,7 +196,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
work->event = event;
work->adev = adev;
- work->crtc_id = amdgpu_crtc->crtc_id;
+ work->crtc_id = amdgpu_crtc->crtc_object_id.id;
/* schedule unpin of the old buffer */
old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
@@ -239,7 +239,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
work->base = base;
- r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id);
+ r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_object_id.id);
if (r) {
DRM_ERROR("failed to get vblank before flip\n");
goto pflip_cleanup;
@@ -259,7 +259,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
- amdgpu_crtc->crtc_id, amdgpu_crtc, work);
+ amdgpu_crtc->crtc_object_id.id, amdgpu_crtc, work);
/* update crtc fb */
crtc->primary->fb = fb;
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
@@ -267,7 +267,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
return 0;
vblank_cleanup:
- drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id);
+ drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_object_id.id);
pflip_cleanup:
if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) {
@@ -181,7 +181,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
crtc = (struct drm_crtc *)minfo->crtcs[i];
if (crtc && crtc->base.id == info->mode_crtc.id) {
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
- ui32 = amdgpu_crtc->crtc_id;
+ ui32 = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
found = 1;
break;
}
@@ -368,7 +368,7 @@ struct amdgpu_atom_ss {
struct amdgpu_crtc {
struct drm_crtc base;
- int crtc_id;
+ struct graphics_object_id crtc_object_id;
u16 lut_r[256], lut_g[256], lut_b[256];
bool enabled;
bool can_tile;
@@ -1162,7 +1162,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
&ddev->mode_config.crtc_list, head) {
amdgpu_crtc = to_amdgpu_crtc(crtc);
if (crtc->enabled) {
- adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
+ adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_object_id.id);
adev->pm.dpm.new_active_crtc_count++;
}
}
@@ -45,10 +45,10 @@ void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc,
SET_CRTC_OVERSCAN_PS_ALLOCATION args;
int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
int a1, a2;
-
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
- args.ucCRTC = amdgpu_crtc->crtc_id;
+ args.ucCRTC = controller_id;
switch (amdgpu_crtc->rmx_type) {
case RMX_CENTER:
@@ -87,10 +87,10 @@ void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc)
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
ENABLE_SCALER_PS_ALLOCATION args;
int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
-
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
- args.ucScaler = amdgpu_crtc->crtc_id;
+ args.ucScaler = controller_id;
switch (amdgpu_crtc->rmx_type) {
case RMX_FULL:
@@ -117,10 +117,10 @@ void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock)
int index =
GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
ENABLE_CRTC_PS_ALLOCATION args;
-
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
- args.ucCRTC = amdgpu_crtc->crtc_id;
+ args.ucCRTC = controller_id;
args.ucEnable = lock;
amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
@@ -133,10 +133,10 @@ void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state)
struct amdgpu_device *adev = dev->dev_private;
int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
ENABLE_CRTC_PS_ALLOCATION args;
-
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
- args.ucCRTC = amdgpu_crtc->crtc_id;
+ args.ucCRTC = controller_id;
args.ucEnable = state;
amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
@@ -149,10 +149,11 @@ void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state)
struct amdgpu_device *adev = dev->dev_private;
int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
BLANK_CRTC_PS_ALLOCATION args;
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
- args.ucCRTC = amdgpu_crtc->crtc_id;
+ args.ucCRTC = controller_id;
args.ucBlanking = state;
amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
@@ -165,10 +166,11 @@ void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state)
struct amdgpu_device *adev = dev->dev_private;
int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
- args.ucDispPipeId = amdgpu_crtc->crtc_id;
+ args.ucDispPipeId = controller_id;
args.ucEnable = state;
amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
@@ -195,6 +197,7 @@ void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc,
SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
u16 misc = 0;
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2));
@@ -226,7 +229,7 @@ void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc,
misc |= ATOM_DOUBLE_CLOCK_MODE;
args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
- args.ucCRTC = amdgpu_crtc->crtc_id;
+ args.ucCRTC = controller_id;
amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
}
@@ -238,14 +241,15 @@ union atom_enable_ss {
};
static void amdgpu_atombios_crtc_program_ss(struct amdgpu_device *adev,
- int enable,
- int pll_id,
- int crtc_id,
- struct amdgpu_atom_ss *ss)
+ int enable,
+ int pll_id,
+ struct graphics_object_id crtc_object_id,
+ struct amdgpu_atom_ss *ss)
{
unsigned i;
int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
union atom_enable_ss args;
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(crtc_object_id);
if (enable) {
/* Don't mess with SS if percentage is 0 or external ss.
@@ -261,7 +265,7 @@ static void amdgpu_atombios_crtc_program_ss(struct amdgpu_device *adev,
for (i = 0; i < adev->mode_info.num_crtc; i++) {
if (adev->mode_info.crtcs[i] &&
adev->mode_info.crtcs[i]->enabled &&
- i != crtc_id &&
+ i != controller_id &&
pll_id == adev->mode_info.crtcs[i]->pll_id) {
/* one other crtc is using this pll don't turn
* off spread spectrum as it might turn off
@@ -521,7 +525,7 @@ static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)
}
void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
- u32 crtc_id,
+ struct graphics_object_id crtc_object_id,
int pll_id,
u32 encoder_mode,
struct graphics_object_id encoder_object_id,
@@ -540,6 +544,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
union set_pixel_clock args;
uint8_t atom_enc_id = amdgpu_encoder_object_to_atom(encoder_object_id);
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(crtc_object_id);
memset(&args, 0, sizeof(args));
@@ -559,7 +564,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
args.v1.ucFracFbDiv = frac_fb_div;
args.v1.ucPostDiv = post_div;
args.v1.ucPpll = pll_id;
- args.v1.ucCRTC = crtc_id;
+ args.v1.ucCRTC = controller_id;
args.v1.ucRefDivSrc = 1;
break;
case 2:
@@ -569,7 +574,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
args.v2.ucFracFbDiv = frac_fb_div;
args.v2.ucPostDiv = post_div;
args.v2.ucPpll = pll_id;
- args.v2.ucCRTC = crtc_id;
+ args.v2.ucCRTC = controller_id;
args.v2.ucRefDivSrc = 1;
break;
case 3:
@@ -579,7 +584,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
args.v3.ucFracFbDiv = frac_fb_div;
args.v3.ucPostDiv = post_div;
args.v3.ucPpll = pll_id;
- if (crtc_id == ATOM_CRTC2)
+ if (controller_id == ATOM_CRTC2)
args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
else
args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
@@ -589,7 +594,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
args.v3.ucEncoderMode = encoder_mode;
break;
case 5:
- args.v5.ucCRTC = crtc_id;
+ args.v5.ucCRTC = controller_id;
args.v5.usPixelClock = cpu_to_le16(clock / 10);
args.v5.ucRefDiv = ref_div;
args.v5.usFbDiv = cpu_to_le16(fb_div);
@@ -620,7 +625,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
args.v5.ucPpll = pll_id;
break;
case 6:
- args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
+ args.v6.ulDispEngClkFreq = cpu_to_le32(controller_id << 24 | clock / 10);
args.v6.ucRefDiv = ref_div;
args.v6.usFbDiv = cpu_to_le16(fb_div);
args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
@@ -775,9 +780,9 @@ void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
&fb_div, &frac_fb_div, &ref_div, &post_div);
amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id,
- amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
+ amdgpu_crtc->crtc_object_id, &amdgpu_crtc->ss);
- amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
+ amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_object_id, amdgpu_crtc->pll_id,
encoder_mode, amdgpu_encoder->encoder_object_id, clock,
ref_div, fb_div, frac_fb_div, post_div,
amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
@@ -800,7 +805,7 @@ void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
amdgpu_crtc->ss.step = step_size;
amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id,
- amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
+ amdgpu_crtc->crtc_object_id, &amdgpu_crtc->ss);
}
}
@@ -38,7 +38,7 @@ void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc,
void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev,
u32 dispclk);
void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
- u32 crtc_id,
+ struct graphics_object_id crtc_object_id,
int pll_id,
u32 encoder_mode,
struct graphics_object_id encoder_object_id,
@@ -1307,7 +1307,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
uint8_t frev, crev;
struct amdgpu_encoder_atom_dig *dig;
enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
-
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
@@ -1318,7 +1318,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
switch (crev) {
case 1:
default:
- args.v1.ucCRTC = amdgpu_crtc->crtc_id;
+ args.v1.ucCRTC = controller_id;
switch (enc_id) {
case ENCODER_ID_INTERNAL_TMDS1:
case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
@@ -1357,7 +1357,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
}
break;
case 2:
- args.v2.ucCRTC = amdgpu_crtc->crtc_id;
+ args.v2.ucCRTC = controller_id;
if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN) {
struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
@@ -1424,7 +1424,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
}
break;
case 3:
- args.v3.ucCRTC = amdgpu_crtc->crtc_id;
+ args.v3.ucCRTC = controller_id;
if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN) {
struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
@@ -802,7 +802,7 @@ static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
struct drm_display_mode *mode)
{
u32 tmp, buffer_alloc, i, mem_cfg;
- u32 pipe_offset = amdgpu_crtc->crtc_id;
+ u32 pipe_offset = amdgpu_crtc->crtc_object_id.id;
/*
* Line Buffer Setup
* There are 6 line buffers, one for each display controllers.
@@ -1760,7 +1760,7 @@ static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
*/
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
- amdgpu_crtc->crtc_id);
+ amdgpu_crtc->crtc_object_id.id);
WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
@@ -2028,12 +2028,13 @@ static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
u32 vga_control;
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
- vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
+ vga_control = RREG32(vga_control_regs[controller_id]) & ~1;
if (enable)
- WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
+ WREG32(vga_control_regs[controller_id], vga_control | 1);
else
- WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
+ WREG32(vga_control_regs[controller_id], vga_control);
}
static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
@@ -2312,7 +2313,7 @@ static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
int i;
u32 tmp;
- DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
+ DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_object_id.id);
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
@@ -2590,7 +2591,7 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
if (!obj) {
- DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
+ DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_object_id.id);
return -ENOENT;
}
@@ -2708,16 +2709,16 @@ static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
dce_v10_0_vga_enable(crtc, false);
/* Make sure VBLANK and PFLIP interrupts are still enabled */
- type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
+ type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_object_id.id);
amdgpu_irq_update(adev, &adev->crtc_irq, type);
amdgpu_irq_update(adev, &adev->pageflip_irq, type);
- drm_vblank_on(dev, amdgpu_crtc->crtc_id);
+ drm_vblank_on(dev, amdgpu_crtc->crtc_object_id.id);
dce_v10_0_crtc_load_lut(crtc);
break;
case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND:
case DRM_MODE_DPMS_OFF:
- drm_vblank_off(dev, amdgpu_crtc->crtc_id);
+ drm_vblank_off(dev, amdgpu_crtc->crtc_object_id.id);
if (amdgpu_crtc->enabled) {
dce_v10_0_vga_enable(crtc, true);
amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
@@ -2777,7 +2778,7 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
for (i = 0; i < adev->mode_info.num_crtc; i++) {
if (adev->mode_info.crtcs[i] &&
adev->mode_info.crtcs[i]->enabled &&
- i != amdgpu_crtc->crtc_id &&
+ i != amdgpu_crtc->crtc_object_id.id &&
amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
/* one other crtc is using this pll don't turn
* off the pll
@@ -2791,7 +2792,7 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
case ATOM_PPLL1:
case ATOM_PPLL2:
/* disable the ppll */
- amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
+ amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_object_id, amdgpu_crtc->pll_id,
0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
default:
@@ -2899,7 +2900,7 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
- amdgpu_crtc->crtc_id = index;
+ amdgpu_crtc->crtc_object_id = display_graphics_object_id_init(index, ENUM_ID_UNKNOWN, OBJECT_TYPE_CONTROLLER);
adev->mode_info.crtcs[index] = amdgpu_crtc;
amdgpu_crtc->max_cursor_width = 128;
@@ -2913,7 +2914,7 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
amdgpu_crtc->lut_b[i] = i << 2;
}
- switch (amdgpu_crtc->crtc_id) {
+ switch (index) {
case 0:
default:
amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
@@ -3375,7 +3376,7 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
+ drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_object_id.id);
schedule_work(&works->unpin_work);
return 0;
@@ -737,7 +737,7 @@ static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
struct drm_display_mode *mode)
{
u32 tmp, buffer_alloc, i, mem_cfg;
- u32 pipe_offset = amdgpu_crtc->crtc_id;
+ u32 pipe_offset = amdgpu_crtc->crtc_object_id.id;
/*
* Line Buffer Setup
* There are 6 line buffers, one for each display controllers.
@@ -1695,7 +1695,7 @@ static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
*/
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
- amdgpu_crtc->crtc_id);
+ amdgpu_crtc->crtc_object_id.id);
WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
@@ -1963,12 +1963,13 @@ static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
u32 vga_control;
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
- vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
+ vga_control = RREG32(vga_control_regs[controller_id]) & ~1;
if (enable)
- WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
+ WREG32(vga_control_regs[controller_id], vga_control | 1);
else
- WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
+ WREG32(vga_control_regs[controller_id], vga_control);
}
static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
@@ -2247,7 +2248,7 @@ static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
int i;
u32 tmp;
- DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
+ DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_object_id.id);
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
@@ -2527,7 +2528,7 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
if (!obj) {
- DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
+ DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_object_id.id);
return -ENOENT;
}
@@ -2645,16 +2646,16 @@ static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
dce_v11_0_vga_enable(crtc, false);
/* Make sure VBLANK and PFLIP interrupts are still enabled */
- type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
+ type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_object_id.id);
amdgpu_irq_update(adev, &adev->crtc_irq, type);
amdgpu_irq_update(adev, &adev->pageflip_irq, type);
- drm_vblank_on(dev, amdgpu_crtc->crtc_id);
+ drm_vblank_on(dev, amdgpu_crtc->crtc_object_id.id);
dce_v11_0_crtc_load_lut(crtc);
break;
case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND:
case DRM_MODE_DPMS_OFF:
- drm_vblank_off(dev, amdgpu_crtc->crtc_id);
+ drm_vblank_off(dev, amdgpu_crtc->crtc_object_id.id);
if (amdgpu_crtc->enabled) {
dce_v11_0_vga_enable(crtc, true);
amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
@@ -2714,7 +2715,7 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
for (i = 0; i < adev->mode_info.num_crtc; i++) {
if (adev->mode_info.crtcs[i] &&
adev->mode_info.crtcs[i]->enabled &&
- i != amdgpu_crtc->crtc_id &&
+ i != amdgpu_crtc->crtc_object_id.id &&
amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
/* one other crtc is using this pll don't turn
* off the pll
@@ -2728,7 +2729,7 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
case ATOM_PPLL1:
case ATOM_PPLL2:
/* disable the ppll */
- amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
+ amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_object_id, amdgpu_crtc->pll_id,
0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
default:
@@ -2836,7 +2837,7 @@ static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
- amdgpu_crtc->crtc_id = index;
+ amdgpu_crtc->crtc_object_id = display_graphics_object_id_init(index, ENUM_ID_UNKNOWN, OBJECT_TYPE_CONTROLLER);
adev->mode_info.crtcs[index] = amdgpu_crtc;
amdgpu_crtc->max_cursor_width = 128;
@@ -2850,7 +2851,7 @@ static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
amdgpu_crtc->lut_b[i] = i << 2;
}
- switch (amdgpu_crtc->crtc_id) {
+ switch (index) {
case 0:
default:
amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
@@ -3317,7 +3318,7 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
+ drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_object_id.id);
schedule_work(&works->unpin_work);
return 0;
@@ -747,7 +747,7 @@ static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
struct drm_display_mode *mode)
{
u32 tmp, buffer_alloc, i;
- u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
+ u32 pipe_offset = amdgpu_crtc->crtc_object_id.id * 0x8;
/*
* Line Buffer Setup
* There are 6 line buffers, one for each display controllers.
@@ -1716,7 +1716,7 @@ static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
*/
- WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
+ WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_object_id.id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
}
@@ -1965,12 +1965,13 @@ static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
u32 vga_control;
+ enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
- vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
+ vga_control = RREG32(vga_control_regs[controller_id]) & ~1;
if (enable)
- WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
+ WREG32(vga_control_regs[controller_id], vga_control | 1);
else
- WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
+ WREG32(vga_control_regs[controller_id], vga_control);
}
static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
@@ -2229,7 +2230,7 @@ static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
struct amdgpu_device *adev = dev->dev_private;
int i;
- DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
+ DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_object_id.id);
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
@@ -2502,7 +2503,7 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
if (!obj) {
- DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
+ DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_object_id.id);
return -ENOENT;
}
@@ -2620,16 +2621,16 @@ static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
dce_v8_0_vga_enable(crtc, false);
/* Make sure VBLANK and PFLIP interrupts are still enabled */
- type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
+ type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_object_id.id);
amdgpu_irq_update(adev, &adev->crtc_irq, type);
amdgpu_irq_update(adev, &adev->pageflip_irq, type);
- drm_vblank_on(dev, amdgpu_crtc->crtc_id);
+ drm_vblank_on(dev, amdgpu_crtc->crtc_object_id.id);
dce_v8_0_crtc_load_lut(crtc);
break;
case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND:
case DRM_MODE_DPMS_OFF:
- drm_vblank_off(dev, amdgpu_crtc->crtc_id);
+ drm_vblank_off(dev, amdgpu_crtc->crtc_object_id.id);
if (amdgpu_crtc->enabled) {
dce_v8_0_vga_enable(crtc, true);
amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
@@ -2689,7 +2690,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
for (i = 0; i < adev->mode_info.num_crtc; i++) {
if (adev->mode_info.crtcs[i] &&
adev->mode_info.crtcs[i]->enabled &&
- i != amdgpu_crtc->crtc_id &&
+ i != amdgpu_crtc->crtc_object_id.id &&
amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
/* one other crtc is using this pll don't turn
* off the pll
@@ -2702,7 +2703,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
case ATOM_PPLL1:
case ATOM_PPLL2:
/* disable the ppll */
- amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
+ amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_object_id, amdgpu_crtc->pll_id,
0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
case ATOM_PPLL0:
@@ -2710,7 +2711,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
if ((adev->asic_type == CHIP_KAVERI) ||
(adev->asic_type == CHIP_BONAIRE) ||
(adev->asic_type == CHIP_HAWAII))
- amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
+ amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_object_id, amdgpu_crtc->pll_id,
0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
default:
@@ -2818,7 +2819,7 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
- amdgpu_crtc->crtc_id = index;
+ amdgpu_crtc->crtc_object_id = display_graphics_object_id_init(index, ENUM_ID_UNKNOWN, OBJECT_TYPE_CONTROLLER);
adev->mode_info.crtcs[index] = amdgpu_crtc;
amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
@@ -2832,7 +2833,7 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
amdgpu_crtc->lut_b[i] = i << 2;
}
- amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
+ amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_object_id.id];
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
amdgpu_crtc->adjusted_clock = 0;
@@ -3384,7 +3385,7 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
+ drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_object_id.id);
schedule_work(&works->unpin_work);
return 0;