@@ -341,7 +341,8 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
ATOM_ENCODER_CAP_RECORD *cap_record;
u16 caps = 0;
-
+ struct graphics_object_id encoder_object_id;
+ encoder_object_id = amdgpu_object_id_from_bios_object_id(encoder_obj);
while (record->ucRecordSize > 0 &&
record->ucRecordType > 0 &&
record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
@@ -355,7 +356,7 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
record = (ATOM_COMMON_RECORD_HEADER *)
((char *)record + record->ucRecordSize);
}
- amdgpu_display_add_encoder(adev, encoder_obj,
+ amdgpu_display_add_encoder(adev, encoder_object_id,
le16_to_cpu(path->usDeviceTag),
caps);
}
@@ -313,7 +313,7 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector)
amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
- ENCODER_OBJECT_ID_NONE) &&
+ ENCODER_ID_UNKNOWN) &&
amdgpu_connector->ddc_bus->has_aux) {
amdgpu_connector->edid = drm_get_edid(connector,
&amdgpu_connector->ddc_bus->aux.ddc);
@@ -1228,7 +1228,7 @@ static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
} else {
/* need to setup ddc on the bridge */
if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
- ENCODER_OBJECT_ID_NONE) {
+ ENCODER_ID_UNKNOWN) {
if (encoder)
amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
}
@@ -1262,7 +1262,7 @@ static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
} else {
/* need to setup ddc on the bridge */
if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
- ENCODER_OBJECT_ID_NONE) {
+ ENCODER_ID_UNKNOWN) {
if (encoder)
amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
}
@@ -1275,11 +1275,12 @@ static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
return ret;
}
-u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
+enum encoder_id amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
{
struct drm_encoder *encoder;
struct amdgpu_encoder *amdgpu_encoder;
int i;
+ enum encoder_id enc_id;
for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
if (connector->encoder_ids[i] == 0)
@@ -1291,17 +1292,17 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn
continue;
amdgpu_encoder = to_amdgpu_encoder(encoder);
-
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_TRAVIS:
- case ENCODER_OBJECT_ID_NUTMEG:
- return amdgpu_encoder->encoder_id;
+ enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
+ switch (enc_id) {
+ case ENCODER_ID_EXTERNAL_TRAVIS:
+ case ENCODER_ID_EXTERNAL_NUTMEG:
+ return enc_id;
default:
break;
}
}
- return ENCODER_OBJECT_ID_NONE;
+ return ENCODER_ID_UNKNOWN;
}
static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
@@ -1383,7 +1384,7 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
amdgpu_atombios_encoder_set_edp_panel_power(connector,
ATOM_TRANSMITTER_ACTION_POWER_OFF);
} else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
- ENCODER_OBJECT_ID_NONE) {
+ ENCODER_ID_UNKNOWN) {
/* DP bridges are always DP */
amdgpu_dig_connector->dp_sink_type = CONNECTOR_ID_DISPLAY_PORT;
/* get the DPCD from the bridge */
@@ -1552,9 +1553,10 @@ amdgpu_connector_add(struct amdgpu_device *adev,
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
amdgpu_encoder = to_amdgpu_encoder(encoder);
if (amdgpu_encoder->devices & supported_device) {
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_TRAVIS:
- case ENCODER_OBJECT_ID_NUTMEG:
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
+ switch (enc_id) {
+ case ENCODER_ID_EXTERNAL_TRAVIS:
+ case ENCODER_ID_EXTERNAL_NUTMEG:
is_dp_bridge = true;
break;
default:
@@ -27,7 +27,7 @@
struct edid *amdgpu_connector_edid(struct drm_connector *connector);
void amdgpu_connector_hotplug(struct drm_connector *connector);
int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector);
-u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
+enum encoder_id amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector);
void
amdgpu_connector_add(struct amdgpu_device *adev,
@@ -341,38 +341,22 @@ static const char *encoder_names[38] = {
"INTERNAL_TMDS2",
"INTERNAL_DAC1",
"INTERNAL_DAC2",
- "INTERNAL_SDVOA",
- "INTERNAL_SDVOB",
- "SI170B",
- "CH7303",
- "CH7301",
- "INTERNAL_DVO1",
- "EXTERNAL_SDVOA",
- "EXTERNAL_SDVOB",
- "TITFP513",
"INTERNAL_LVTM1",
- "VT1623",
- "HDMI_SI1930",
- "HDMI_INTERNAL",
+ "INTERNAL_HDMI",
"INTERNAL_KLDSCP_TMDS1",
- "INTERNAL_KLDSCP_DVO1",
"INTERNAL_KLDSCP_DAC1",
"INTERNAL_KLDSCP_DAC2",
- "SI178",
"MVPU_FPGA",
"INTERNAL_DDI",
- "VT1625",
- "HDMI_SI1932",
- "DP_AN9801",
- "DP_DP501",
"INTERNAL_UNIPHY",
"INTERNAL_KLDSCP_LVTMA",
"INTERNAL_UNIPHY1",
"INTERNAL_UNIPHY2",
"NUTMEG",
"TRAVIS",
- "INTERNAL_VCE",
+ "INTERNAL_WIRELESS",
"INTERNAL_UNIPHY3",
+ "INTERNAL_VIRTUAL",
};
static const char *hpd_names[6] = {
@@ -429,31 +413,33 @@ void amdgpu_print_display_setup(struct drm_device *dev)
}
DRM_INFO(" Encoders:\n");
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ enum encoder_id enc_id;
amdgpu_encoder = to_amdgpu_encoder(encoder);
devices = amdgpu_encoder->devices & amdgpu_connector->devices;
+ enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (devices) {
if (devices & ATOM_DEVICE_CRT1_SUPPORT)
- DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" CRT1: %s\n", encoder_names[enc_id]);
if (devices & ATOM_DEVICE_CRT2_SUPPORT)
- DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" CRT2: %s\n", encoder_names[enc_id]);
if (devices & ATOM_DEVICE_LCD1_SUPPORT)
- DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" LCD1: %s\n", encoder_names[enc_id]);
if (devices & ATOM_DEVICE_DFP1_SUPPORT)
- DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" DFP1: %s\n", encoder_names[enc_id]);
if (devices & ATOM_DEVICE_DFP2_SUPPORT)
- DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" DFP2: %s\n", encoder_names[enc_id]);
if (devices & ATOM_DEVICE_DFP3_SUPPORT)
- DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" DFP3: %s\n", encoder_names[enc_id]);
if (devices & ATOM_DEVICE_DFP4_SUPPORT)
- DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" DFP4: %s\n", encoder_names[enc_id]);
if (devices & ATOM_DEVICE_DFP5_SUPPORT)
- DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" DFP5: %s\n", encoder_names[enc_id]);
if (devices & ATOM_DEVICE_DFP6_SUPPORT)
- DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" DFP6: %s\n", encoder_names[enc_id]);
if (devices & ATOM_DEVICE_TV1_SUPPORT)
- DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" TV1: %s\n", encoder_names[enc_id]);
if (devices & ATOM_DEVICE_CV_SUPPORT)
- DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
+ DRM_INFO(" CV: %s\n", encoder_names[enc_id]);
}
}
i++;
@@ -132,16 +132,16 @@ u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
if (other_encoder) {
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(other_encoder);
-
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_TRAVIS:
- case ENCODER_OBJECT_ID_NUTMEG:
- return amdgpu_encoder->encoder_id;
+ uint8_t enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
+ switch (enc_id) {
+ case ENCODER_ID_EXTERNAL_TRAVIS:
+ case ENCODER_ID_EXTERNAL_NUTMEG:
+ return enc_id;
default:
- return ENCODER_OBJECT_ID_NONE;
+ return ENCODER_ID_UNKNOWN;
}
}
- return ENCODER_OBJECT_ID_NONE;
+ return ENCODER_ID_UNKNOWN;
}
void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
@@ -85,6 +85,77 @@ static enum connector_id connector_id_from_bios_object_id(uint32_t bios_object_i
return id;
}
+static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
+{
+ uint32_t bios_encoder_id = gpu_id_from_bios_object_id(bios_object_id);
+ enum encoder_id id;
+
+ switch (bios_encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+ id = ENCODER_ID_INTERNAL_LVDS;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+ id = ENCODER_ID_INTERNAL_TMDS1;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_TMDS2:
+ id = ENCODER_ID_INTERNAL_TMDS2;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DAC1:
+ id = ENCODER_ID_INTERNAL_DAC1;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+ id = ENCODER_ID_INTERNAL_DAC2;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+ id = ENCODER_ID_INTERNAL_LVTM1;
+ break;
+ case ENCODER_OBJECT_ID_HDMI_INTERNAL:
+ id = ENCODER_ID_INTERNAL_HDMI;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+ id = ENCODER_ID_INTERNAL_KLDSCP_TMDS1;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+ id = ENCODER_ID_INTERNAL_KLDSCP_DAC1;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ id = ENCODER_ID_INTERNAL_KLDSCP_DAC2;
+ break;
+ case ENCODER_OBJECT_ID_MVPU_FPGA:
+ id = ENCODER_ID_EXTERNAL_MVPU_FPGA;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DDI:
+ id = ENCODER_ID_INTERNAL_DDI;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ id = ENCODER_ID_INTERNAL_UNIPHY;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+ id = ENCODER_ID_INTERNAL_KLDSCP_LVTMA;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ id = ENCODER_ID_INTERNAL_UNIPHY1;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ id = ENCODER_ID_INTERNAL_UNIPHY2;
+ break;
+ case ENCODER_OBJECT_ID_ALMOND: /* ENCODER_OBJECT_ID_NUTMEG */
+ id = ENCODER_ID_EXTERNAL_NUTMEG;
+ break;
+ case ENCODER_OBJECT_ID_TRAVIS:
+ id = ENCODER_ID_EXTERNAL_TRAVIS;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ id = ENCODER_ID_INTERNAL_UNIPHY3;
+ break;
+ default:
+ id = ENCODER_ID_UNKNOWN;
+ break;
+ }
+
+ return id;
+}
+
static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id)
{
uint32_t bios_enum_id =
@@ -157,6 +228,8 @@ static uint32_t id_from_bios_object_id(enum object_type type,
switch (type) {
case OBJECT_TYPE_CONNECTOR:
return (uint32_t)connector_id_from_bios_object_id(bios_object_id);
+ case OBJECT_TYPE_ENCODER:
+ return (uint32_t)encoder_id_from_bios_object_id(bios_object_id);
default:
return 0;
}
@@ -181,3 +254,59 @@ struct graphics_object_id amdgpu_object_id_from_bios_object_id(uint32_t bios_obj
return go_id;
}
+
+uint8_t amdgpu_encoder_id_to_atom(enum encoder_id id)
+{
+ switch (id) {
+ case ENCODER_ID_INTERNAL_LVDS:
+ return ENCODER_OBJECT_ID_INTERNAL_LVDS;
+ case ENCODER_ID_INTERNAL_TMDS1:
+ return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
+ case ENCODER_ID_INTERNAL_TMDS2:
+ return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
+ case ENCODER_ID_INTERNAL_DAC1:
+ return ENCODER_OBJECT_ID_INTERNAL_DAC1;
+ case ENCODER_ID_INTERNAL_DAC2:
+ return ENCODER_OBJECT_ID_INTERNAL_DAC2;
+ case ENCODER_ID_INTERNAL_LVTM1:
+ return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
+ case ENCODER_ID_INTERNAL_HDMI:
+ return ENCODER_OBJECT_ID_HDMI_INTERNAL;
+ case ENCODER_ID_EXTERNAL_TRAVIS:
+ return ENCODER_OBJECT_ID_TRAVIS;
+ case ENCODER_ID_EXTERNAL_NUTMEG:
+ return ENCODER_OBJECT_ID_NUTMEG;
+ case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
+ return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
+ return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
+ return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
+ case ENCODER_ID_EXTERNAL_MVPU_FPGA:
+ return ENCODER_OBJECT_ID_MVPU_FPGA;
+ case ENCODER_ID_INTERNAL_DDI:
+ return ENCODER_OBJECT_ID_INTERNAL_DDI;
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
+ case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
+ return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
+ case ENCODER_ID_INTERNAL_UNIPHY2:
+ return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
+ case ENCODER_ID_INTERNAL_UNIPHY3:
+ return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
+ case ENCODER_ID_INTERNAL_WIRELESS:
+ return ENCODER_OBJECT_ID_INTERNAL_VCE;
+ case ENCODER_ID_UNKNOWN:
+ return ENCODER_OBJECT_ID_NONE;
+ default:
+ return ENCODER_OBJECT_ID_NONE;
+ }
+}
+
+uint8_t amdgpu_encoder_object_to_atom(struct graphics_object_id object_id)
+{
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(object_id);
+ return amdgpu_encoder_id_to_atom(enc_id);
+}
@@ -290,7 +290,7 @@ struct amdgpu_display_funcs {
u32 *vbl, u32 *position);
/* display topology setup */
void (*add_encoder)(struct amdgpu_device *adev,
- uint32_t encoder_enum,
+ struct graphics_object_id encoder_id,
uint32_t supported_device,
u16 caps);
void (*add_connector)(struct amdgpu_device *adev,
@@ -432,8 +432,7 @@ struct amdgpu_encoder_atom_dig {
struct amdgpu_encoder {
struct drm_encoder base;
- uint32_t encoder_enum;
- uint32_t encoder_id;
+ struct graphics_object_id encoder_object_id;
uint32_t devices;
uint32_t active_device;
uint32_t flags;
@@ -595,4 +594,6 @@ extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
/* amdgpu_grph_object_id_helpers.c */
struct graphics_object_id amdgpu_object_id_from_bios_object_id(uint32_t bios_object_id);
+uint8_t amdgpu_encoder_object_to_atom(struct graphics_object_id object_id);
+uint8_t amdgpu_encoder_id_to_atom(enum encoder_id id);
#endif
@@ -319,11 +319,11 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,
union adjust_pixel_clock args;
u8 frev, crev;
int index;
-
+ uint8_t atom_enc_id;
amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV;
if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
- (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
+ (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN)) {
if (connector) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
struct amdgpu_connector_atom_dig *dig_connector =
@@ -368,6 +368,7 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,
}
}
+ atom_enc_id = amdgpu_encoder_object_to_atom(amdgpu_encoder->encoder_object_id);
/* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
* accordingly based on the encoder/transmitter to work around
* special hw requirements.
@@ -385,7 +386,7 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,
case 1:
case 2:
args.v1.usPixelClock = cpu_to_le16(clock / 10);
- args.v1.ucTransmitterID = amdgpu_encoder->encoder_id;
+ args.v1.ucTransmitterID = atom_enc_id;
args.v1.ucEncodeMode = encoder_mode;
if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
args.v1.ucConfig |=
@@ -397,7 +398,7 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,
break;
case 3:
args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
- args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id;
+ args.v3.sInput.ucTransmitterID = atom_enc_id;
args.v3.sInput.ucEncodeMode = encoder_mode;
args.v3.sInput.ucDispPllConfig = 0;
if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
@@ -418,9 +419,9 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,
DISPPLL_CONFIG_DUAL_LINK;
}
if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
- ENCODER_OBJECT_ID_NONE)
+ ENCODER_ID_UNKNOWN)
args.v3.sInput.ucExtTransmitterID =
- amdgpu_encoder_get_dp_bridge_encoder_id(encoder);
+ amdgpu_encoder_id_to_atom(amdgpu_encoder_get_dp_bridge_encoder_id(encoder));
else
args.v3.sInput.ucExtTransmitterID = 0;
@@ -523,7 +524,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
u32 crtc_id,
int pll_id,
u32 encoder_mode,
- u32 encoder_id,
+ struct graphics_object_id encoder_object_id,
u32 clock,
u32 ref_div,
u32 fb_div,
@@ -538,6 +539,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
u8 frev, crev;
int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
union set_pixel_clock args;
+ uint8_t atom_enc_id = amdgpu_encoder_object_to_atom(encoder_object_id);
memset(&args, 0, sizeof(args));
@@ -583,7 +585,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
- args.v3.ucTransmitterId = encoder_id;
+ args.v3.ucTransmitterId = atom_enc_id;
args.v3.ucEncoderMode = encoder_mode;
break;
case 5:
@@ -613,7 +615,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
break;
}
}
- args.v5.ucTransmitterID = encoder_id;
+ args.v5.ucTransmitterID = atom_enc_id;
args.v5.ucEncoderMode = encoder_mode;
args.v5.ucPpll = pll_id;
break;
@@ -645,7 +647,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
break;
}
}
- args.v6.ucTransmitterID = encoder_id;
+ args.v6.ucTransmitterID = atom_enc_id;
args.v6.ucEncoderMode = encoder_mode;
args.v6.ucPpll = pll_id;
break;
@@ -676,7 +678,7 @@ int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc,
amdgpu_crtc->ss_enabled = false;
if ((amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
- (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
+ (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_ID_UNKNOWN)) {
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
struct drm_connector *connector =
amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder);
@@ -776,7 +778,7 @@ void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
- encoder_mode, amdgpu_encoder->encoder_id, clock,
+ encoder_mode, amdgpu_encoder->encoder_object_id, clock,
ref_div, fb_div, frac_fb_div, post_div,
amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
@@ -41,7 +41,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
u32 crtc_id,
int pll_id,
u32 encoder_mode,
- u32 encoder_id,
+ struct graphics_object_id encoder_object_id,
u32 clock,
u32 ref_div,
u32 fb_div,
@@ -266,7 +266,7 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector
unsigned lane_num, i, max_pix_clock;
if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
- ENCODER_OBJECT_ID_NUTMEG) {
+ ENCODER_ID_EXTERNAL_NUTMEG) {
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
max_pix_clock = (lane_num * 270000 * 8) / bpp;
if (max_pix_clock >= pix_clock) {
@@ -373,14 +373,14 @@ int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
dig_connector = amdgpu_connector->con_priv;
- if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
+ if (dp_bridge != ENCODER_ID_UNKNOWN) {
/* DP bridge chips */
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
if (tmp & 1)
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
- else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
- (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
+ else if ((dp_bridge == ENCODER_ID_EXTERNAL_NUTMEG) ||
+ (dp_bridge == ENCODER_ID_EXTERNAL_TRAVIS))
panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
else
panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
@@ -89,15 +89,16 @@ amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encode
if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
amdgpu_encoder->enc_priv) {
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
dig = amdgpu_encoder->enc_priv;
dig->backlight_level = level;
amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, dig->backlight_level);
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
if (dig->backlight_level == 0)
amdgpu_atombios_encoder_setup_dig_transmitter(encoder,
ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
@@ -271,11 +272,12 @@ void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *encoder)
bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
return true;
default:
return false;
@@ -304,7 +306,7 @@ bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder *encoder,
amdgpu_panel_mode_fixup(encoder, adjusted_mode);
if ((amdgpu_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
- (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
+ (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN)) {
struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
amdgpu_atombios_dp_set_link_config(connector, adjusted_mode);
}
@@ -320,18 +322,20 @@ amdgpu_atombios_encoder_setup_dac(struct drm_encoder *encoder, int action)
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
DAC_ENCODER_CONTROL_PS_ALLOCATION args;
int index = 0;
-
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
memset(&args, 0, sizeof(args));
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_DAC1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_DAC1:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
break;
- case ENCODER_OBJECT_ID_INTERNAL_DAC2:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ case ENCODER_ID_INTERNAL_DAC2:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
break;
+ default:
+ return;
}
args.ucAction = action;
@@ -375,7 +379,7 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder)
struct amdgpu_connector_atom_dig *dig_connector;
/* dp bridges are always DP */
- if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
+ if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN)
return ATOM_ENCODER_MODE_DP;
connector = amdgpu_get_connector_for_encoder(encoder);
@@ -503,6 +507,7 @@ amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder,
int dp_clock = 0;
int dp_lane_count = 0;
int hpd_id = AMDGPU_HPD_NONE;
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (connector) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
@@ -543,17 +548,19 @@ amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder,
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
break;
+ default:
+ break;
}
if (dig->linkb)
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
@@ -655,6 +662,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
int igp_lane_info = 0;
int dig_encoder = dig->dig_encoder;
int hpd_id = AMDGPU_HPD_NONE;
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
connector = amdgpu_get_connector_for_encoder_init(encoder);
@@ -690,16 +698,18 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
memset(&args, 0, sizeof(args));
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+ case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
break;
+ default:
+ return;
}
if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
@@ -732,7 +742,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
if ((adev->flags & AMD_IS_APU) &&
- (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
+ (enc_id == ENCODER_ID_INTERNAL_UNIPHY)) {
if (is_dp ||
!amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) {
if (igp_lane_info & 0x1)
@@ -785,16 +795,18 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
if (dig->linkb)
args.v2.acConfig.ucLinkSel = 1;
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
args.v2.acConfig.ucTransmitterSel = 0;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
args.v2.acConfig.ucTransmitterSel = 1;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
args.v2.acConfig.ucTransmitterSel = 2;
break;
+ default:
+ return;
}
if (is_dp) {
@@ -845,16 +857,18 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
else
args.v3.acConfig.ucRefClkSource = pll_id;
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
args.v3.acConfig.ucTransmitterSel = 0;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
args.v3.acConfig.ucTransmitterSel = 1;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
args.v3.acConfig.ucTransmitterSel = 2;
break;
+ default:
+ return;
}
if (is_dp)
@@ -907,16 +921,18 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
} else
args.v4.acConfig.ucRefClkSource = pll_id;
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
args.v4.acConfig.ucTransmitterSel = 0;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
args.v4.acConfig.ucTransmitterSel = 1;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
args.v4.acConfig.ucTransmitterSel = 2;
break;
+ default:
+ return;
}
if (is_dp)
@@ -935,28 +951,30 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
else
args.v5.usSymClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
if (dig->linkb)
args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
else
args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
if (dig->linkb)
args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
else
args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
if (dig->linkb)
args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
else
args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
break;
+ default:
+ return;
}
if (is_dp)
args.v5.ucLaneNum = dp_lane_count;
@@ -1061,7 +1079,7 @@ amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder *encoder,
int dp_clock = 0;
int dp_lane_count = 0;
int connector_object_id = 0;
- u32 ext_enum = (ext_amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
+ enum object_enum_id ext_enum = ext_amdgpu_encoder->encoder_object_id.enum_id;
if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
connector = amdgpu_get_connector_for_encoder_init(encoder);
@@ -1125,15 +1143,17 @@ amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder *encoder,
else
args.v3.sExtEncoder.ucLaneNum = 4;
switch (ext_enum) {
- case GRAPH_OBJECT_ENUM_ID1:
+ case ENUM_ID_1:
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
break;
- case GRAPH_OBJECT_ENUM_ID2:
+ case ENUM_ID_2:
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
break;
- case GRAPH_OBJECT_ENUM_ID3:
+ case ENUM_ID_3:
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
break;
+ default:
+ return;
}
args.v3.sExtEncoder.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
break;
@@ -1232,15 +1252,15 @@ void
amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
-
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
- amdgpu_encoder->encoder_id, mode, amdgpu_encoder->devices,
+ enc_id, mode, amdgpu_encoder->devices,
amdgpu_encoder->active_device);
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
switch (mode) {
case DRM_MODE_DPMS_ON:
amdgpu_atombios_encoder_setup_dig(encoder, ATOM_ENABLE);
@@ -1252,7 +1272,7 @@ amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode)
break;
}
break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
switch (mode) {
case DRM_MODE_DPMS_ON:
amdgpu_atombios_encoder_setup_dac(encoder, ATOM_ENABLE);
@@ -1286,6 +1306,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
uint8_t frev, crev;
struct amdgpu_encoder_atom_dig *dig;
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
memset(&args, 0, sizeof(args));
@@ -1298,23 +1319,23 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
case 1:
default:
args.v1.ucCRTC = amdgpu_crtc->crtc_id;
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_TMDS1:
+ case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
break;
- case ENCODER_OBJECT_ID_INTERNAL_LVDS:
- case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+ case ENCODER_ID_INTERNAL_LVDS:
+ case ENCODER_ID_INTERNAL_LVTM1:
if (amdgpu_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
else
args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
break;
- case ENCODER_OBJECT_ID_INTERNAL_DDI:
+ case ENCODER_ID_INTERNAL_DDI:
args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
break;
- case ENCODER_OBJECT_ID_INTERNAL_DAC1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+ case ENCODER_ID_INTERNAL_DAC1:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
@@ -1322,8 +1343,8 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
else
args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
break;
- case ENCODER_OBJECT_ID_INTERNAL_DAC2:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ case ENCODER_ID_INTERNAL_DAC2:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
@@ -1331,11 +1352,13 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
else
args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
break;
+ default:
+ return;
}
break;
case 2:
args.v2.ucCRTC = amdgpu_crtc->crtc_id;
- if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
+ if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN) {
struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
@@ -1349,12 +1372,12 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
} else {
args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
}
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
+ case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
dig = amdgpu_encoder->enc_priv;
switch (dig->dig_encoder) {
case 0:
@@ -1380,7 +1403,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
break;
}
break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
@@ -1388,7 +1411,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
else
args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
@@ -1396,11 +1419,13 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
else
args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
break;
+ default:
+ return;
}
break;
case 3:
args.v3.ucCRTC = amdgpu_crtc->crtc_id;
- if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
+ if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN) {
struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
@@ -1415,12 +1440,12 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
}
args.v3.ucDstBpc = amdgpu_atombios_encoder_get_bpc(encoder);
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
+ case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
dig = amdgpu_encoder->enc_priv;
switch (dig->dig_encoder) {
case 0:
@@ -1446,7 +1471,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
break;
}
break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
@@ -1454,7 +1479,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
else
args.v3.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
@@ -1462,6 +1487,8 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
else
args.v3.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
break;
+ default:
+ break;
}
break;
}
@@ -1484,15 +1511,17 @@ amdgpu_atombios_encoder_init_dig(struct amdgpu_device *adev)
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder);
-
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
amdgpu_atombios_encoder_setup_dig_transmitter(encoder, ATOM_TRANSMITTER_ACTION_INIT,
0, 0);
break;
+ default:
+ return;
}
if (ext_encoder)
@@ -1509,6 +1538,7 @@ amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder *encoder,
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
ATOM_DEVICE_CV_SUPPORT |
@@ -1524,8 +1554,8 @@ amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder *encoder,
args.sDacload.ucMisc = 0;
- if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
- (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
+ if ((enc_id == ENCODER_ID_INTERNAL_DAC1) ||
+ (enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC1))
args.sDacload.ucDacType = ATOM_DAC_A;
else
args.sDacload.ucDacType = ATOM_DAC_B;
@@ -1811,7 +1841,7 @@ amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder)
union lvds_info *lvds_info;
uint8_t frev, crev;
struct amdgpu_encoder_atom_dig *lvds = NULL;
- int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
+ enum object_enum_id encoder_enum = encoder->encoder_object_id.enum_id;
if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
&frev, &crev, &data_offset)) {
@@ -1867,7 +1897,7 @@ amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder)
encoder->native_mode = lvds->native_mode;
- if (encoder_enum == 2)
+ if (encoder_enum == ENUM_ID_2)
lvds->linkb = true;
else
lvds->linkb = false;
@@ -1943,7 +1973,7 @@ amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder)
struct amdgpu_encoder_atom_dig *
amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder)
{
- int encoder_enum = (amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
+ enum object_enum_id encoder_enum = amdgpu_encoder->encoder_object_id.enum_id;
struct amdgpu_encoder_atom_dig *dig = kzalloc(sizeof(struct amdgpu_encoder_atom_dig), GFP_KERNEL);
if (!dig)
@@ -1953,7 +1983,7 @@ amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder)
dig->coherent_mode = true;
dig->dig_encoder = -1;
- if (encoder_enum == 2)
+ if (encoder_enum == ENUM_ID_2)
dig->linkb = true;
else
dig->linkb = false;
@@ -716,6 +716,7 @@ static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
int bpc = 0;
u32 tmp = 0;
enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (connector) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
@@ -728,8 +729,8 @@ static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
return;
/* not needed for analog */
- if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
- (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
+ if ((enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC1) ||
+ (enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC2))
return;
if (bpc == 0)
@@ -1973,7 +1974,7 @@ static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
dig->afmt->enabled = enable;
DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
- enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
+ enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_object_id.id);
}
static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
@@ -2387,31 +2388,31 @@ static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
if (dig->linkb)
return 1;
else
return 0;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
if (dig->linkb)
return 3;
else
- return 2;
- break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ return 2; break;
+ case ENCODER_ID_INTERNAL_UNIPHY2:
if (dig->linkb)
return 5;
else
return 4;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
return 6;
break;
default:
- DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
+ DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_object_id.id);
return 0;
}
}
@@ -2791,7 +2792,7 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
case ATOM_PPLL2:
/* disable the ppll */
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
- 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
+ 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
default:
break;
@@ -3547,7 +3548,7 @@ static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
if ((amdgpu_encoder->active_device &
(ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
(amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
- ENCODER_OBJECT_ID_NONE)) {
+ ENCODER_ID_UNKNOWN)) {
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
if (dig) {
dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
@@ -3676,9 +3677,9 @@ static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
};
static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
- uint32_t encoder_enum,
- uint32_t supported_device,
- u16 caps)
+ struct graphics_object_id encoder_object_id,
+ uint32_t supported_device,
+ u16 caps)
{
struct drm_device *dev = adev->ddev;
struct drm_encoder *encoder;
@@ -3687,7 +3688,8 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
/* see if we already added it */
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
amdgpu_encoder = to_amdgpu_encoder(encoder);
- if (amdgpu_encoder->encoder_enum == encoder_enum) {
+ if (display_graphics_object_id_is_equal_unchecked(amdgpu_encoder->encoder_object_id,
+ encoder_object_id)) {
amdgpu_encoder->devices |= supported_device;
return;
}
@@ -3718,25 +3720,24 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
amdgpu_encoder->enc_priv = NULL;
- amdgpu_encoder->encoder_enum = encoder_enum;
- amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+ amdgpu_encoder->encoder_object_id = encoder_object_id;
amdgpu_encoder->devices = supported_device;
amdgpu_encoder->rmx_type = RMX_OFF;
amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
amdgpu_encoder->is_ext_encoder = false;
amdgpu_encoder->caps = caps;
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ switch (encoder_object_id.id) {
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
DRM_MODE_ENCODER_DAC, NULL);
drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
amdgpu_encoder->rmx_type = RMX_FULL;
drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
@@ -3753,8 +3754,8 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
}
drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
break;
- case ENCODER_OBJECT_ID_TRAVIS:
- case ENCODER_OBJECT_ID_NUTMEG:
+ case ENCODER_ID_EXTERNAL_TRAVIS:
+ case ENCODER_ID_EXTERNAL_NUTMEG:
/* these are handled by the primary encoders */
amdgpu_encoder->is_ext_encoder = true;
if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
@@ -651,6 +651,7 @@ static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
int bpc = 0;
u32 tmp = 0;
enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (connector) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
@@ -663,8 +664,8 @@ static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
return;
/* not needed for analog */
- if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
- (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
+ if ((enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC1) ||
+ (enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC2))
return;
if (bpc == 0)
@@ -1908,7 +1909,7 @@ static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
dig->afmt->enabled = enable;
DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
- enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
+ enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_object_id.id);
}
static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
@@ -2313,31 +2314,32 @@ static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
if (dig->linkb)
return 1;
else
return 0;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
if (dig->linkb)
return 3;
else
return 2;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
if (dig->linkb)
return 5;
else
return 4;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
return 6;
break;
default:
- DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
+ DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_object_id.id);
return 0;
}
}
@@ -2727,7 +2729,7 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
case ATOM_PPLL2:
/* disable the ppll */
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
- 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
+ 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
default:
break;
@@ -3488,7 +3490,7 @@ static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
if ((amdgpu_encoder->active_device &
(ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
(amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
- ENCODER_OBJECT_ID_NONE)) {
+ ENCODER_ID_UNKNOWN)) {
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
if (dig) {
dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
@@ -3617,9 +3619,9 @@ static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
};
static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
- uint32_t encoder_enum,
- uint32_t supported_device,
- u16 caps)
+ struct graphics_object_id encoder_object_id,
+ uint32_t supported_device,
+ u16 caps)
{
struct drm_device *dev = adev->ddev;
struct drm_encoder *encoder;
@@ -3628,7 +3630,8 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
/* see if we already added it */
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
amdgpu_encoder = to_amdgpu_encoder(encoder);
- if (amdgpu_encoder->encoder_enum == encoder_enum) {
+ if (display_graphics_object_id_is_equal_unchecked(amdgpu_encoder->encoder_object_id,
+ encoder_object_id)) {
amdgpu_encoder->devices |= supported_device;
return;
}
@@ -3659,25 +3662,24 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
amdgpu_encoder->enc_priv = NULL;
- amdgpu_encoder->encoder_enum = encoder_enum;
- amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+ amdgpu_encoder->encoder_object_id = encoder_object_id;
amdgpu_encoder->devices = supported_device;
amdgpu_encoder->rmx_type = RMX_OFF;
amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
amdgpu_encoder->is_ext_encoder = false;
amdgpu_encoder->caps = caps;
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ switch (encoder_object_id.id) {
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
DRM_MODE_ENCODER_DAC, NULL);
drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
amdgpu_encoder->rmx_type = RMX_FULL;
drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
@@ -3694,8 +3696,8 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
}
drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
break;
- case ENCODER_OBJECT_ID_TRAVIS:
- case ENCODER_OBJECT_ID_NUTMEG:
+ case ENCODER_ID_EXTERNAL_TRAVIS:
+ case ENCODER_ID_EXTERNAL_NUTMEG:
/* these are handled by the primary encoders */
amdgpu_encoder->is_ext_encoder = true;
if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
@@ -664,6 +664,7 @@ static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
int bpc = 0;
u32 tmp = 0;
enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (connector) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
@@ -676,8 +677,8 @@ static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
return;
/* not needed for analog */
- if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
- (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
+ if ((enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC1) ||
+ (enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC2))
return;
if (bpc == 0)
@@ -1910,7 +1911,7 @@ static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
dig->afmt->enabled = enable;
DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
- enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
+ enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_object_id.id);
}
static int dce_v8_0_afmt_init(struct amdgpu_device *adev)
@@ -2288,31 +2289,31 @@ static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
-
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
+ switch (enc_id) {
+ case ENCODER_ID_INTERNAL_UNIPHY:
if (dig->linkb)
return 1;
else
return 0;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
if (dig->linkb)
return 3;
else
return 2;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
if (dig->linkb)
return 5;
else
return 4;
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
return 6;
break;
default:
- DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
+ DRM_ERROR("invalid encoder_id: 0x%x\n", enc_id);
return 0;
}
}
@@ -2702,7 +2703,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
case ATOM_PPLL2:
/* disable the ppll */
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
- 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
+ 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
case ATOM_PPLL0:
/* disable the ppll */
@@ -2710,7 +2711,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
(adev->asic_type == CHIP_BONAIRE) ||
(adev->asic_type == CHIP_HAWAII))
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
- 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
+ 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
default:
break;
@@ -3477,7 +3478,7 @@ static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
if ((amdgpu_encoder->active_device &
(ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
(amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
- ENCODER_OBJECT_ID_NONE)) {
+ ENCODER_ID_UNKNOWN)) {
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
if (dig) {
dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
@@ -3606,7 +3607,7 @@ static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
};
static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
- uint32_t encoder_enum,
+ struct graphics_object_id encoder_object_id,
uint32_t supported_device,
u16 caps)
{
@@ -3617,11 +3618,11 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
/* see if we already added it */
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
amdgpu_encoder = to_amdgpu_encoder(encoder);
- if (amdgpu_encoder->encoder_enum == encoder_enum) {
+ if (display_graphics_object_id_is_equal_unchecked(amdgpu_encoder->encoder_object_id,
+ encoder_object_id)) {
amdgpu_encoder->devices |= supported_device;
return;
}
-
}
/* add a new one */
@@ -3648,25 +3649,24 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
amdgpu_encoder->enc_priv = NULL;
- amdgpu_encoder->encoder_enum = encoder_enum;
- amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+ amdgpu_encoder->encoder_object_id = encoder_object_id;
amdgpu_encoder->devices = supported_device;
amdgpu_encoder->rmx_type = RMX_OFF;
amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
amdgpu_encoder->is_ext_encoder = false;
amdgpu_encoder->caps = caps;
- switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+ switch (encoder_object_id.id) {
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
DRM_MODE_ENCODER_DAC, NULL);
drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
break;
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ case ENCODER_ID_INTERNAL_UNIPHY:
+ case ENCODER_ID_INTERNAL_UNIPHY1:
+ case ENCODER_ID_INTERNAL_UNIPHY2:
+ case ENCODER_ID_INTERNAL_UNIPHY3:
if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
amdgpu_encoder->rmx_type = RMX_FULL;
drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
@@ -3683,8 +3683,8 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
}
drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
break;
- case ENCODER_OBJECT_ID_TRAVIS:
- case ENCODER_OBJECT_ID_NUTMEG:
+ case ENCODER_ID_EXTERNAL_TRAVIS:
+ case ENCODER_ID_EXTERNAL_NUTMEG:
/* these are handled by the primary encoders */
amdgpu_encoder->is_ext_encoder = true;
if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
@@ -315,4 +315,5 @@ static inline uint32_t display_graphics_object_id_to_uint(struct graphics_object
return object_id;
}
+#define DISPLAY_NO_OBJECT (struct graphics_object_id){0}
#endif