From patchwork Thu Apr 21 08:58:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8897571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A01CEBF440 for ; Thu, 21 Apr 2016 08:59:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C6C1220303 for ; Thu, 21 Apr 2016 08:59:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id ECB1320211 for ; Thu, 21 Apr 2016 08:59:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F19E06EC35; Thu, 21 Apr 2016 08:59:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 861736EC14 for ; Thu, 21 Apr 2016 08:59:36 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id e201so15935685wme.2 for ; Thu, 21 Apr 2016 01:59:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=nvSH/2vs2/fVG3b2E5aDqFLMYyljSiag+6mET85/cxE=; b=MqXn2wMJAR/PbXsQtlnZ9Ffd1uYGqS/5lQcv84YrbdDC9GZ/vM4oGQgWJ/jiXP6Os9 oJk8brq1+mgWwtNVQUC1zVD5wUWfmj5wOWis+Y1LsvxAaW1kN39gYukLcDmnfb3YvguW pX/A5Jlx2pvZRhBlnFksjE1gDHBIWk59Y6Irrac0vQAcnag3vit74NcvLNataL60Y2Xr QDVxSs+cCWiECF6he/x5kFMsoX0yZgR5UEC2L4jM6+h/uzeq8ayItM4FK4KN8q3KesrV uAhjKCvbNIPSIprIwx8MGXFRJqvZCrbkzmQ4x5vwJX1kgvL4fRvOwIei9ntbP5gRZrVn 9/Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=nvSH/2vs2/fVG3b2E5aDqFLMYyljSiag+6mET85/cxE=; b=AmeelL7LxHp+pVKF5hU7tmUuAQnKpWocBTDmTyyIrMNj5ilNHOlQ2OnhAiH0IMhX6L CKAPE6GlOG6ZwT/1V94NXMk7WYyEvXnjVGXWFqUB2VSuk6sUiaqFqMV1lbwI/tjYrYq4 KgFIMT0MbcXJ3h6rNN4aA84cBvxRGhm52x/RT+KS3jblvLZYJsXhsT7fjYFS3HJB+jGw TwgBwDoZFwLE9dJAX2tv+C4ta0gDa4d3WDvEGJFqNKmRZA/VdQBi/+PXXTrJvJVylYna btiMtOO+Bv141suYhOWB9SujXqtHInNWx78RNAP1XhBdPoe8OhRPxAntnk1WSVGLxDQF EwKw== X-Gm-Message-State: AOPr4FXcXgMKT29bu/HPGuGh2X71J9eOtuxq913jQO8bzQhsy7adiEAQrRzVQodNBatLVQ== X-Received: by 10.28.46.19 with SMTP id u19mr12831892wmu.98.1461229174985; Thu, 21 Apr 2016 01:59:34 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id wa1sm1710773wjc.45.2016.04.21.01.59.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Apr 2016 01:59:34 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 21 Apr 2016 09:58:57 +0100 Message-Id: <1461229148-2939-8-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461229148-2939-1-git-send-email-chris@chris-wilson.co.uk> References: <1461229148-2939-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 08/19] drm/i915: Consolidate L3 remapping LRI X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We can use a single MI_LOAD_REGISTER_IMM command packet to write all the L3 remapping registers, shrinking the number of bytes required to emit the context switch. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_context.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 7b0a82c0d6e0..1c63bea32211 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -603,16 +603,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) { + u32 *remap_info = req->i915->l3_parity.remap_info[slice]; struct intel_engine_cs *engine = req->engine; - struct drm_device *dev = engine->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; int i, ret; - if (!HAS_L3_DPF(dev) || !remap_info) + if (!remap_info) return 0; - ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); + ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); if (ret) return ret; @@ -621,15 +619,15 @@ int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) * here because no other code should access these registers other than * at initialization time. */ - for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { - intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); + for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); intel_ring_emit(engine, remap_info[i]); } - + intel_ring_emit(engine, MI_NOOP); intel_ring_advance(engine); - return ret; + return 0; } static inline bool skip_rcs_switch(struct intel_engine_cs *engine,