From patchwork Thu Apr 21 08:59:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8897621 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 345C1BF29F for ; Thu, 21 Apr 2016 09:00:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3EC01202FF for ; Thu, 21 Apr 2016 09:00:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BB66120303 for ; Thu, 21 Apr 2016 09:00:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F4546EC34; Thu, 21 Apr 2016 08:59:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9183F6EC33 for ; Thu, 21 Apr 2016 08:59:47 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id l6so19818499wml.3 for ; Thu, 21 Apr 2016 01:59:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=t1SQM7FxOX6Zx2FM6xdg4UShqqjPYyasZaWwG7in8d0=; b=M9NYP/EobOOCzRGGRDVhROgFgW33c+eXE+Du1JWezfsidKEVh0tp6rULqVOfjILvMt yxYBtZ3IDy95z/ppThc2INMTUt21ZQjwOAHWNgp9MsAmTWoIMp9ryyQAx9+AnpW2Dm33 JaiwqFNtGui6TJEbE+Rh6jcyqJO3Gx7KJ4wYO3T6r6jOUYTKRhkZNeElkE9IvomU+X3g Hp19B38TzkDSDCCwdfpwbRawtA0z7bqnOoASO2mIxBX8b67fmQrFc4EzCmWAfHmdvZBl KeDKTWCrnV2yHXQkQF0wLcs4BXZcOZnM9IVQzVXNR+6Da5TWHJQwLI03WaNATqPZ6AfT YENg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=t1SQM7FxOX6Zx2FM6xdg4UShqqjPYyasZaWwG7in8d0=; b=WFWEu+eBZRP4k70+4HPKX0nQQns6Nw9DeP6IkQZEfBpwF+htCWp2UHnzr/scZrZJiG Rg8ZdWqOJISW/gCP36cPkRzMYpTzvFYR04eNzsukBWoShvBPuI5cRPME3DZnDPHQsAZ2 AlSMqp5HqBaMknihf6JXe19XfSJS5kLBgqikMc7I9pz5oohj5sfps23RU3u6lUhdXuFg 4TxGzBDxm/6eI0x/BTQPxNYsGb/MlD31sPD3yMhnaJ8cI2wxnXdIuxOYbvw3MRrwNM6Z oEtnx8DzyR058wQhdE7C0eCyxjAwk6+gg6cGe7hnj07FHfdqZPoayVXzwLvPd+gHbMSt lzjw== X-Gm-Message-State: AOPr4FU5GnMTJl7b6oiXEbUBdC70sqkxnzRnHSRD32rQsCAQyvUAAyCwIaE5yn2P5c4JKw== X-Received: by 10.28.64.197 with SMTP id n188mr33044074wma.96.1461229185924; Thu, 21 Apr 2016 01:59:45 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id wa1sm1710773wjc.45.2016.04.21.01.59.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Apr 2016 01:59:44 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 21 Apr 2016 09:59:04 +0100 Message-Id: <1461229148-2939-15-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461229148-2939-1-git-send-email-chris@chris-wilson.co.uk> References: <1461229148-2939-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 15/19] drm/i915: Move the magical deferred context allocation into the request X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We can hide more details of execlists from higher level code by removing the explicit call to create an execlist context from execbuffer and into its first use by execlists. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 -------- drivers/gpu/drm/i915/intel_lrc.c | 23 +++++++++++++++-------- drivers/gpu/drm/i915/intel_lrc.h | 2 -- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 6f4f2a6cdf93..e0ee5d1ac372 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1085,14 +1085,6 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, return ERR_PTR(-EIO); } - if (i915.enable_execlists && !ctx->engine[engine->id].state) { - int ret = intel_lr_context_deferred_alloc(ctx, engine); - if (ret) { - DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); - return ERR_PTR(ret); - } - } - return ctx; } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index eeb8be695288..23bc5fca6595 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -227,6 +227,8 @@ enum { #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 +static int execlists_context_deferred_alloc(struct intel_context *ctx, + struct intel_engine_cs *engine); static int intel_lr_context_pin(struct intel_context *ctx, struct intel_engine_cs *engine); @@ -675,8 +677,6 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request struct intel_engine_cs *engine = request->engine; int ret; - request->ringbuf = request->ctx->engine[engine->id].ringbuf; - if (i915.enable_guc_submission) { /* * Check that the GuC has space for the request before @@ -690,6 +690,14 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request return ret; } + if (request->ctx->engine[engine->id].state == NULL) { + ret = execlists_context_deferred_alloc(request->ctx, engine); + if (ret) + return ret; + } + + request->ringbuf = request->ctx->engine[engine->id].ringbuf; + ret = intel_lr_context_pin(request->ctx, engine); if (ret) return ret; @@ -2134,7 +2142,7 @@ logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine) if (ret) goto error; - ret = intel_lr_context_deferred_alloc(dctx, engine); + ret = execlists_context_deferred_alloc(dctx, engine); if (ret) goto error; @@ -2608,9 +2616,9 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine) } /** - * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context + * execlists_context_deferred_alloc() - create the LRC specific bits of a context * @ctx: LR context to create. - * @ring: engine to be used with the context. + * @engine: engine to be used with the context. * * This function can be called more than once, with different engines, if we plan * to use the context with them. The context backing objects and the ringbuffers @@ -2620,9 +2628,8 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine) * * Return: non-zero on error. */ - -int intel_lr_context_deferred_alloc(struct intel_context *ctx, - struct intel_engine_cs *engine) +static int execlists_context_deferred_alloc(struct intel_context *ctx, + struct intel_engine_cs *engine) { struct drm_device *dev = engine->dev; struct drm_i915_gem_object *ctx_obj; diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index b17ab79333aa..8bea937973f6 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -102,8 +102,6 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf, void intel_lr_context_free(struct intel_context *ctx); uint32_t intel_lr_context_size(struct intel_engine_cs *engine); -int intel_lr_context_deferred_alloc(struct intel_context *ctx, - struct intel_engine_cs *engine); void intel_lr_context_unpin(struct intel_context *ctx, struct intel_engine_cs *engine);