@@ -42,4 +42,44 @@
clock-frequency = <32768>;
};
};
+
+ pwm_dfll: pwm@70110000 {
+ compatible = "nvidia,tegra210-dfll-pwm";
+ reg = <0x0 0x70110000 0x0 0x400>;
+ clocks = <&tegra_car TEGRA210_CLK_DFLL_REF>;
+ clock-names = "ref";
+ #pwm-cells = <2>;
+ pwm-regulator = <&cpu_ovr_reg>;
+ status = "disable";
+ };
+
+ pwm_regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu_ovr_reg: pwm-regulator@0 {
+ status = "okay";
+ reg = <0>;
+ compatible = "pwm-regulator";
+ pwms = <&pwm_dfll 0 2500>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <708000>;
+ regulator-max-microvolt = <1322400>;
+ regulator-always-on;
+ regulator-boot-on;
+ voltage-table =
+ <708000 0>, <727200 1>, <746400 2>,
+ <765600 3>, <784800 4>, <804000 5>,
+ <823200 6>, <842400 7>, <861600 8>,
+ <880800 9>, <900000 10>, <919200 11>,
+ <938400 12>, <957600 13>, <976800 14>,
+ <996000 15>, <1015200 16>, <1034400 17>,
+ <1053600 18>, <1072800 19>, <1092000 20>,
+ <1111200 21>, <1130400 22>, <1149600 23>,
+ <1168800 24>, <1188000 25>, <1207200 26>,
+ <1226400 27>, <1245600 28>, <1264800 29>,
+ <1284000 30>, <1303200 31>, <1322400 32>;
+ };
+ };
};
@@ -6,4 +6,27 @@
/ {
model = "NVIDIA Jetson TX1 Developer Kit";
compatible = "nvidia,p2371-2180", "nvidia,tegra210";
+
+ pinmux: pinmux@700008d4 {
+ dvfs_pwm_active_state: dvfs_pwm_active {
+ dvfs_pwm_pbb1 {
+ nvidia,pins = "dvfs_pwm_pbb1";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ };
+
+ dvfs_pwm_inactive_state: dvfs_pwm_inactive {
+ dvfs_pwm_pbb1 {
+ nvidia,pins = "dvfs_pwm_pbb1";
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
+ pwm_dfll: pwm@70110000 {
+ status = "okay";
+ pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
+ pinctrl-0 = <&dvfs_pwm_active_state>;
+ pinctrl-1 = <&dvfs_pwm_inactive_state>;
+ };
};
The CPU rail on Jetson TX1 is supplied by a Open Voltage Regulator (OVR) which is controlled by PWM signals, and the PWM signals are generated by DFLL PWM controller. So this patch adds DFLL_PWM device-tree node and a PWM regulator node for the OVR. Signed-off-by: Penny Chiu <pchiu@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 40 ++++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 23 +++++++++++++ 2 files changed, 63 insertions(+)