From patchwork Sun Apr 24 07:31:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8919991 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BD2789F1C1 for ; Sun, 24 Apr 2016 07:32:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B9F7F20222 for ; Sun, 24 Apr 2016 07:32:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C0E012022D for ; Sun, 24 Apr 2016 07:32:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 746C06E1AF; Sun, 24 Apr 2016 07:32:18 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 25C7F6E159 for ; Sun, 24 Apr 2016 07:32:13 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id e201so14195314wme.2 for ; Sun, 24 Apr 2016 00:32:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=t1SQM7FxOX6Zx2FM6xdg4UShqqjPYyasZaWwG7in8d0=; b=Ten2pVmyrY9ComMrM7iua9GYMYRfLbHcHOwKl+i+P4zlVixVj+vIls+6IGAm4Z9XYN gg/377WYw+OiE/1ujlKoWu1N/pbwx3ifYz11RAI1hjcyQY0I1vvoPQS5hkRe4VTeF/Fi 9sE1KCBuZxzNo2SY9gpUtMvQRexuNDav0wtWTjSmD3GlK+6uGGjFlpHfPIsSxMecGm9k nJPmp/UnNnB4cONnQb7KSUs0s5YPtSyknyePJgjtuXd2eKGPPU9yoh5IYrkRBgH9mEq4 r1KAKM89bU53iZCR6DxeUX7ikJYwQ7RV75JF2Y7H+BD+l1MDQhNesbHOrSUF/ICEMlAa 48Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=t1SQM7FxOX6Zx2FM6xdg4UShqqjPYyasZaWwG7in8d0=; b=PRXbVFWEv6CZHfp28RzMGZtqa22Ix0S7gE36ssiFrbEOFZPcPuwapb+uukcbu0CiWI maJA8eJBBqgCUPneUr0hIoXr1cn2wS7hpzqOPzNWwRowI0ouJaPQTUWMghcceuI0QfxZ 5Zn72jKBkkmWZs1T7CPUV/Tr7yqVRDOQBYgO3GP6+NZQU2R5zfU9p/RRlwigPhUL5/K2 msBZ7GT5+hwP8YgVkj4cmGV+7Fe/PSZKYt79cE6ekwse6jmbFrs+fgmJX85yuJTLlXx3 w0RBWMnqTmai2emx91O6qmEvWMXxLlcZhK98dkFvY6CWfGUy53RKm3EkeVTbjSr9pe/p gAzQ== X-Gm-Message-State: AOPr4FWMEMgaPtUPgSojz7mw+V5XXTYcoNWfVuOyMmGufHt7ZOV5gC4+TlR4K/UJMXbAbw== X-Received: by 10.28.211.75 with SMTP id k72mr6100727wmg.77.1461483131649; Sun, 24 Apr 2016 00:32:11 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id c4sm16964833wjm.24.2016.04.24.00.32.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 24 Apr 2016 00:32:10 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Sun, 24 Apr 2016 08:31:36 +0100 Message-Id: <1461483101-10618-16-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461483101-10618-1-git-send-email-chris@chris-wilson.co.uk> References: <1461483101-10618-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH v2 16/21] drm/i915: Move the magical deferred context allocation into the request X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We can hide more details of execlists from higher level code by removing the explicit call to create an execlist context from execbuffer and into its first use by execlists. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 -------- drivers/gpu/drm/i915/intel_lrc.c | 23 +++++++++++++++-------- drivers/gpu/drm/i915/intel_lrc.h | 2 -- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 6f4f2a6cdf93..e0ee5d1ac372 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1085,14 +1085,6 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, return ERR_PTR(-EIO); } - if (i915.enable_execlists && !ctx->engine[engine->id].state) { - int ret = intel_lr_context_deferred_alloc(ctx, engine); - if (ret) { - DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); - return ERR_PTR(ret); - } - } - return ctx; } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index eeb8be695288..23bc5fca6595 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -227,6 +227,8 @@ enum { #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 +static int execlists_context_deferred_alloc(struct intel_context *ctx, + struct intel_engine_cs *engine); static int intel_lr_context_pin(struct intel_context *ctx, struct intel_engine_cs *engine); @@ -675,8 +677,6 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request struct intel_engine_cs *engine = request->engine; int ret; - request->ringbuf = request->ctx->engine[engine->id].ringbuf; - if (i915.enable_guc_submission) { /* * Check that the GuC has space for the request before @@ -690,6 +690,14 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request return ret; } + if (request->ctx->engine[engine->id].state == NULL) { + ret = execlists_context_deferred_alloc(request->ctx, engine); + if (ret) + return ret; + } + + request->ringbuf = request->ctx->engine[engine->id].ringbuf; + ret = intel_lr_context_pin(request->ctx, engine); if (ret) return ret; @@ -2134,7 +2142,7 @@ logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine) if (ret) goto error; - ret = intel_lr_context_deferred_alloc(dctx, engine); + ret = execlists_context_deferred_alloc(dctx, engine); if (ret) goto error; @@ -2608,9 +2616,9 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine) } /** - * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context + * execlists_context_deferred_alloc() - create the LRC specific bits of a context * @ctx: LR context to create. - * @ring: engine to be used with the context. + * @engine: engine to be used with the context. * * This function can be called more than once, with different engines, if we plan * to use the context with them. The context backing objects and the ringbuffers @@ -2620,9 +2628,8 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine) * * Return: non-zero on error. */ - -int intel_lr_context_deferred_alloc(struct intel_context *ctx, - struct intel_engine_cs *engine) +static int execlists_context_deferred_alloc(struct intel_context *ctx, + struct intel_engine_cs *engine) { struct drm_device *dev = engine->dev; struct drm_i915_gem_object *ctx_obj; diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index b17ab79333aa..8bea937973f6 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -102,8 +102,6 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf, void intel_lr_context_free(struct intel_context *ctx); uint32_t intel_lr_context_size(struct intel_engine_cs *engine); -int intel_lr_context_deferred_alloc(struct intel_context *ctx, - struct intel_engine_cs *engine); void intel_lr_context_unpin(struct intel_context *ctx, struct intel_engine_cs *engine);