From patchwork Sun Apr 24 07:31:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8920091 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F03E8BF29F for ; Sun, 24 Apr 2016 07:32:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EE09F20219 for ; Sun, 24 Apr 2016 07:32:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 123E5201FA for ; Sun, 24 Apr 2016 07:32:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 91C096E1A8; Sun, 24 Apr 2016 07:32:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7E1086E355 for ; Sun, 24 Apr 2016 07:32:19 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id e201so14195624wme.2 for ; Sun, 24 Apr 2016 00:32:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ih91w8YafB+mfQ62k8U3R8izUQrXiHtF5ULTitLAcgA=; b=pN/QpnnQFzCrzPJLW3MfcEjyePfnE6lg3ysHjFleLqr0NciZoyNt7Mm7PfT52mjlrY qLW/SWf6RiM6uIq+np6fGgI1uxDmF0ZXoIZONkRiDZ0PwaTBRV511fWzyxI79pxcrU93 HkQNB0hXt6MyHYBdGVcwSekWKgHnqENC0Lo7FoSbrpjog+1hoax09Yi4tYNvql+6WIM1 IzKNghyE8F2BmA96/bO2U0R50853MG6iUQALLvTw5JG9RCikqNUW/J3fRmZAl9we5Wlu TzDTxBID15InRBnimCEh8GDcxw5po4ZVc+E6BR8WHuhgcijOhLLFqrfihpT1tVM0LVxC u6Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Ih91w8YafB+mfQ62k8U3R8izUQrXiHtF5ULTitLAcgA=; b=SOiyJfzzKQG4KjcgmYoEwxjuJlnAYj2/Sf0Hv9NkOgH9wEGw+3CMZc63QtseWgFclp O2I/opB3GvT2vm9MZUto3+wTn1mMxAcb6nG4XSe0OkslYSXT3AvWh6AEdkH9OGDwhZY3 A8Vq+yEsrbzQfDgoDNbzITQNcN2Nkb4fsM6u91KeK4ZjGqMW+yQ1QWdAITDNrRvskqiJ UA6pVRvCPv/w/n0u0aRw3FYcBZrdaKV92Cm38OgoQIP4eh/mO4W3IgFPdLa/0InOhyeq 70qLGH2kyS7ILA2DsKGT8SCBFlXNR3KamtX+IvOf11L6qo56XUB9xL1c6/LceN4dtpGv qBNg== X-Gm-Message-State: AOPr4FXXHkO8b3LsMeA4F+GXHaPbuiedi4gQ6ynaJmVDMyA9D+GfUzWdb7BEqz3Qpoeu2Q== X-Received: by 10.194.92.163 with SMTP id cn3mr28208939wjb.3.1461483137808; Sun, 24 Apr 2016 00:32:17 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id c4sm16964833wjm.24.2016.04.24.00.32.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 24 Apr 2016 00:32:16 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Sun, 24 Apr 2016 08:31:41 +0100 Message-Id: <1461483101-10618-21-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461483101-10618-1-git-send-email-chris@chris-wilson.co.uk> References: <1461483101-10618-1-git-send-email-chris@chris-wilson.co.uk> Cc: Mika Kuoppala Subject: [Intel-gfx] [PATCH v2 21/21] drm/i915: Unify GPU resets upon shutdown X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As we initialise engines, then contexts, ideally we want to unwind in the opposite order: contexts then engines. Until now, the engines and contexts were tightly coupled (the engine owned the default context) preventing the "natural ordering" during shutdown. Now that execlists merely holds a reference, as does the device for the kernel context, we can relax the ordering constraint upon unload. In doing so, we can reveal the true goal of this patch: always reset the GPU back to its default starting condition before shutdown. It is known that to disable the current legacy context we have to reset the GPU. The same is true when the GPU has been enabled for execlists. However, we do each reset separately, but functionally they are the same: Before shutting down, we need to reset the GPU so that the next hardware user finds the GPU in its expected default settings. This unifies the resets added in a647828afc (drm/i915: Also perform gpu reset under execlist mode) and 8e96d9c4d9 (drm/i915: reset the GPU on context fini). Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin CC: Joonas Lahtinen Cc: Mika Kuoppala Cc: "Niu, Bing" --- drivers/gpu/drm/i915/i915_dma.c | 37 ++++++++++++++++++++++++++------- drivers/gpu/drm/i915/i915_gem.c | 8 ------- drivers/gpu/drm/i915/i915_gem_context.c | 8 +------ 3 files changed, 30 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 5c7615041b31..9aa4346b111a 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -425,6 +425,33 @@ static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { .can_switch = i915_switcheroo_can_switch, }; +static void i915_gem_fini(struct drm_device *dev) +{ + /* + * Neither the BIOS, ourselves or any other kernel + * expects the system to be in execlists mode on startup, + * so we need to reset the GPU back to legacy mode. And the only + * known way to disable logical contexts is through a GPU reset. + * + * So in order to leave the system in a known default configuration, + * always reset the GPU upon unload. In the future, this will also + * cleans up the GEM state tracking, flushing off the requests and + * leaving the system in a known idle state. + * + * Note that is of the upmost importance that the GPU is idle and + * all stray writes are flushed *before* we dismantle the backing + * storage for the pinned objects. + */ + intel_gpu_reset(dev, ALL_ENGINES); + + mutex_lock(&dev->struct_mutex); + i915_gem_context_fini(dev); + i915_gem_cleanup_engines(dev); + mutex_unlock(&dev->struct_mutex); + + WARN_ON(!list_empty(&to_i915(dev)->context_list)); +} + static int i915_load_modeset_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -506,10 +533,7 @@ static int i915_load_modeset_init(struct drm_device *dev) return 0; cleanup_gem: - mutex_lock(&dev->struct_mutex); - i915_gem_cleanup_engines(dev); - i915_gem_context_fini(dev); - mutex_unlock(&dev->struct_mutex); + i915_gem_fini(dev); cleanup_irq: intel_guc_ucode_fini(dev); drm_irq_uninstall(dev); @@ -1456,10 +1480,7 @@ int i915_driver_unload(struct drm_device *dev) flush_workqueue(dev_priv->wq); intel_guc_ucode_fini(dev); - mutex_lock(&dev->struct_mutex); - i915_gem_cleanup_engines(dev); - i915_gem_context_fini(dev); - mutex_unlock(&dev->struct_mutex); + i915_gem_fini(dev); intel_fbc_cleanup_cfb(dev_priv); intel_power_domains_fini(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a88aa7f11a9c..82e41eeb36bb 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4970,14 +4970,6 @@ i915_gem_cleanup_engines(struct drm_device *dev) for_each_engine(engine, dev_priv) dev_priv->gt.cleanup_engine(engine); - - if (i915.enable_execlists) - /* - * Neither the BIOS, ourselves or any other kernel - * expects the system to be in execlists mode on startup, - * so we need to reset the GPU back to legacy mode. - */ - intel_gpu_reset(dev, ALL_ENGINES); } static void diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index fef33a3ce3b7..26122de365b2 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -452,14 +452,8 @@ void i915_gem_context_fini(struct drm_device *dev) i915_gem_context_lost(dev_priv); - if (dctx->legacy_hw_ctx.rcs_state) { - /* The only known way to stop the gpu from accessing the hw context is - * to reset it. Do this as the very last operation to avoid confusing - * other code, leading to spurious errors. */ - intel_gpu_reset(dev, ALL_ENGINES); - + if (dctx->legacy_hw_ctx.rcs_state) i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); - } i915_gem_context_unreference(dctx); dev_priv->kernel_context = NULL;