From patchwork Sun Apr 24 18:10:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8920661 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8D7E19F1C1 for ; Sun, 24 Apr 2016 18:11:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B24BD202AE for ; Sun, 24 Apr 2016 18:11:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D86F020270 for ; Sun, 24 Apr 2016 18:11:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 144B76E418; Sun, 24 Apr 2016 18:11:08 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 61A556E215 for ; Sun, 24 Apr 2016 18:10:43 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id r12so16912359wme.0 for ; Sun, 24 Apr 2016 11:10:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=nvSH/2vs2/fVG3b2E5aDqFLMYyljSiag+6mET85/cxE=; b=c7kk/CzsCYMsDHSbzGFB6dzYpKX01yj9PoKFlVCZws45kpmTo9kJ/T3aLW67ZMlkDd Y5p1iQflpq1MpQDOkNmfTcBEHP3LfE14HNMDYdJVmOISD72xcEB5iZON23/SwUZsjmLp gRDFetkP7TE2yZYbdeUofaj1W5W/6MdNGIvKV3SNnW1PCeFYFOlX4Fc+ATSg7hE+pqts EzM4QttHiIyZ/mRvN/d9eD/5yMthYNE4LHmHzHkKiCVIqAsyxDvDPX4NjzvGJLeUBDYg VIoKrt6FfFQaIDDiGc3XEU6WpetZMPUaTE2B/HmIv7XNS/1XylR0BYEDfPlgSylBYY8M x+hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=nvSH/2vs2/fVG3b2E5aDqFLMYyljSiag+6mET85/cxE=; b=O4U0HstwZZSkzI8fbisH3OXGQFKs/96B8GOmSiilwMoPI4yX+Zo6ExaUguQXgv0AmX ZE+lMoGF5phsMvd/Hr9SQ5Ir4A6KG2CP7yKPXW6cfqhxAA/on9mu1YD23l/mzdKGryV8 mfN2LXTGdwKbTPh+wZak4vK72l+DvbSgsHMJ3UBBSO5mZzgAYFGtFXYVY7LoBGYuVoib 3AetHt4n0jQaA/MTy/NjSosE8ELSUpnSVvcCy8zQBaDjru7XuvnsjAlb/xArqX4pJvHN xmyLxBdjEBbaDsPQ97pxw7K4cww2WWDR+lVJFBrHjVhxwIJVv3EuH83XEtX+I5k1X2+W NBRg== X-Gm-Message-State: AOPr4FVmLVaiD9oqHL74FuYRPkSwq/BSKSrIQnyLivYOiivQuXv8bCG8qw1pA5hSdt8UdQ== X-Received: by 10.28.6.140 with SMTP id 134mr8057169wmg.23.1461521441325; Sun, 24 Apr 2016 11:10:41 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id lh1sm19590888wjb.20.2016.04.24.11.10.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 Apr 2016 11:10:39 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Sun, 24 Apr 2016 19:10:07 +0100 Message-Id: <1461521419-18086-9-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461521419-18086-1-git-send-email-chris@chris-wilson.co.uk> References: <1461521419-18086-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH v3 09/21] drm/i915: Consolidate L3 remapping LRI X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We can use a single MI_LOAD_REGISTER_IMM command packet to write all the L3 remapping registers, shrinking the number of bytes required to emit the context switch. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_context.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 7b0a82c0d6e0..1c63bea32211 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -603,16 +603,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) { + u32 *remap_info = req->i915->l3_parity.remap_info[slice]; struct intel_engine_cs *engine = req->engine; - struct drm_device *dev = engine->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; int i, ret; - if (!HAS_L3_DPF(dev) || !remap_info) + if (!remap_info) return 0; - ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); + ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); if (ret) return ret; @@ -621,15 +619,15 @@ int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) * here because no other code should access these registers other than * at initialization time. */ - for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { - intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); + for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); intel_ring_emit(engine, remap_info[i]); } - + intel_ring_emit(engine, MI_NOOP); intel_ring_advance(engine); - return ret; + return 0; } static inline bool skip_rcs_switch(struct intel_engine_cs *engine,