| Message ID | 1461609378-467-1-git-send-email-caleb@crome.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Apr 25, 2016 at 3:36 PM, Caleb Crome <caleb@crome.org> wrote: > The CCSR_SSI_SOR is a register that clears the TX and/or the RX fifo > on the i.MX SSI port. The fsl_ssi_trigger writes this register in > order to clear the fifo at trigger time. > > However, since the CCSR_SSI_SOR register is not in the volatile list, > the caching mechanism prevented the register write in the trigger > function. This caused the fifo to not be cleared (because the value > was unchanged from the last time the register was written), and thus > causes the channels in both TDM or simple I2S mode to slip and be in > the wrong time slots on SSI restart. > > This has gone unnoticed for so long because with simple stereo mode, > the consequence is that left and right are swapped, which isn't that > noticeable. However, it's catestrophic in some systems that > require the channels to be in the right slots. > > Signed-off-by: Caleb Crome <caleb@crome.org> > Suggested-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
On Mon, Apr 25, 2016 at 11:36:18AM -0700, Caleb Crome wrote: > The CCSR_SSI_SOR is a register that clears the TX and/or the RX fifo > on the i.MX SSI port. The fsl_ssi_trigger writes this register in > order to clear the fifo at trigger time. > > However, since the CCSR_SSI_SOR register is not in the volatile list, > the caching mechanism prevented the register write in the trigger > function. This caused the fifo to not be cleared (because the value > was unchanged from the last time the register was written), and thus > causes the channels in both TDM or simple I2S mode to slip and be in > the wrong time slots on SSI restart. > > This has gone unnoticed for so long because with simple stereo mode, > the consequence is that left and right are swapped, which isn't that > noticeable. However, it's catestrophic in some systems that > require the channels to be in the right slots. > > Signed-off-by: Caleb Crome <caleb@crome.org> > Suggested-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Thanks > > --- > sound/soc/fsl/fsl_ssi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c > index 216e3cb..2f3bf9c 100644 > --- a/sound/soc/fsl/fsl_ssi.c > +++ b/sound/soc/fsl/fsl_ssi.c > @@ -151,6 +151,7 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) > case CCSR_SSI_SACDAT: > case CCSR_SSI_SATAG: > case CCSR_SSI_SACCST: > + case CCSR_SSI_SOR: > return true; > default: > return false; > -- > 1.9.1 >
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 216e3cb..2f3bf9c 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -151,6 +151,7 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) case CCSR_SSI_SACDAT: case CCSR_SSI_SATAG: case CCSR_SSI_SACCST: + case CCSR_SSI_SOR: return true; default: return false;
The CCSR_SSI_SOR is a register that clears the TX and/or the RX fifo on the i.MX SSI port. The fsl_ssi_trigger writes this register in order to clear the fifo at trigger time. However, since the CCSR_SSI_SOR register is not in the volatile list, the caching mechanism prevented the register write in the trigger function. This caused the fifo to not be cleared (because the value was unchanged from the last time the register was written), and thus causes the channels in both TDM or simple I2S mode to slip and be in the wrong time slots on SSI restart. This has gone unnoticed for so long because with simple stereo mode, the consequence is that left and right are swapped, which isn't that noticeable. However, it's catestrophic in some systems that require the channels to be in the right slots. Signed-off-by: Caleb Crome <caleb@crome.org> Suggested-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com> --- sound/soc/fsl/fsl_ssi.c | 1 + 1 file changed, 1 insertion(+)