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[v4,2/6] ASoC: fsl_ssi: The IPG/5 limitation concerns the bitclk, not the sysclk.

Message ID 1462277640-20052-3-git-send-email-arnaud.mouiche@invoxia.com (mailing list archive)
State New, archived
Headers show

Commit Message

Arnaud Mouiche May 3, 2016, 12:13 p.m. UTC
im6sl reference manual 47.7.4:
"
Bit clock - Used to serially clock the data bits in and out of the SSI port.
This clock is either generated internally (from SSI's sys clock) or taken
from external clock source (through the Tx/Rx clock ports).
[...]
Care should be taken to ensure that the bit clock frequency (either
internally generated by dividing the SSI's sys clock or sourced from
external device through Tx/Rx clock ports) is never greater than 1/5
of the ipg_clk (from CCM) frequency.
"

Since, in master mode, the sysclk is a multiple of bitclk, we can
easily reach a high sysclk value, whereas keeping a reasonable bitclk.

ex: 8ch x 16bit x 48kHz = 6144000, requires a 24576000 sysclk (PM=1)
    yet ipg_clk/5 = 66Mhz/5 = 13.2

Signed-off-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com>
---
 sound/soc/fsl/fsl_ssi.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

Comments

Fabio Estevam May 3, 2016, 12:23 p.m. UTC | #1
On Tue, May 3, 2016 at 9:13 AM, Arnaud Mouiche
<arnaud.mouiche@invoxia.com> wrote:
> im6sl reference manual 47.7.4:
> "
> Bit clock - Used to serially clock the data bits in and out of the SSI port.
> This clock is either generated internally (from SSI's sys clock) or taken
> from external clock source (through the Tx/Rx clock ports).
> [...]
> Care should be taken to ensure that the bit clock frequency (either
> internally generated by dividing the SSI's sys clock or sourced from
> external device through Tx/Rx clock ports) is never greater than 1/5
> of the ipg_clk (from CCM) frequency.
> "
>
> Since, in master mode, the sysclk is a multiple of bitclk, we can
> easily reach a high sysclk value, whereas keeping a reasonable bitclk.
>
> ex: 8ch x 16bit x 48kHz = 6144000, requires a 24576000 sysclk (PM=1)
>     yet ipg_clk/5 = 66Mhz/5 = 13.2
>
> Signed-off-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Caleb Crome May 10, 2016, 4:33 p.m. UTC | #2
On Tue, May 3, 2016 at 5:23 AM, Fabio Estevam <festevam@gmail.com> wrote:
> On Tue, May 3, 2016 at 9:13 AM, Arnaud Mouiche
> <arnaud.mouiche@invoxia.com> wrote:
>> im6sl reference manual 47.7.4:
>> "
>> Bit clock - Used to serially clock the data bits in and out of the SSI port.
>> This clock is either generated internally (from SSI's sys clock) or taken
>> from external clock source (through the Tx/Rx clock ports).
>> [...]
>> Care should be taken to ensure that the bit clock frequency (either
>> internally generated by dividing the SSI's sys clock or sourced from
>> external device through Tx/Rx clock ports) is never greater than 1/5
>> of the ipg_clk (from CCM) frequency.
>> "
>>
>> Since, in master mode, the sysclk is a multiple of bitclk, we can
>> easily reach a high sysclk value, whereas keeping a reasonable bitclk.
>>
>> ex: 8ch x 16bit x 48kHz = 6144000, requires a 24576000 sysclk (PM=1)
>>     yet ipg_clk/5 = 66Mhz/5 = 13.2
>>
>> Signed-off-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com>
>
> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Caleb Crome <caleb@crome.org>
diff mbox

Patch

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 472141f..1a9d0ad 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -671,6 +671,15 @@  static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
 	if (IS_ERR(ssi_private->baudclk))
 		return -EINVAL;
 
+	/*
+	 * Hardware limitation: The bclk rate must be
+	 * never greater than 1/5 IPG clock rate
+	 */
+	if (freq * 5 > clk_get_rate(ssi_private->clk)) {
+		dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n");
+		return -EINVAL;
+	}
+
 	baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
 
 	/* It should be already enough to divide clock by setting pm alone */
@@ -687,13 +696,6 @@  static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
 		else
 			clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
 
-		/*
-		 * Hardware limitation: The bclk rate must be
-		 * never greater than 1/5 IPG clock rate
-		 */
-		if (clkrate * 5 > clk_get_rate(ssi_private->clk))
-			continue;
-
 		clkrate /= factor;
 		afreq = clkrate / (i + 1);