From patchwork Wed May 4 21:08:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 9018831 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CC5469F1D3 for ; Wed, 4 May 2016 21:12:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E0401203B4 for ; Wed, 4 May 2016 21:12:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B492E203E6 for ; Wed, 4 May 2016 21:12:52 +0000 (UTC) Received: from localhost ([::1]:50303 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay46C-0003at-OH for patchwork-qemu-devel@patchwork.kernel.org; Wed, 04 May 2016 17:12:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45768) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay44O-0000Mm-BM for qemu-devel@nongnu.org; Wed, 04 May 2016 17:11:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ay44C-0000Yv-3m for qemu-devel@nongnu.org; Wed, 04 May 2016 17:10:50 -0400 Received: from smtp1-g21.free.fr ([212.27.42.1]:32311) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay44B-0000SF-DR for qemu-devel@nongnu.org; Wed, 04 May 2016 17:10:44 -0400 Received: from Quad.localdomain (unknown [IPv6:2a01:e34:eeee:5240:12c3:7bff:fe6b:9a76]) by smtp1-g21.free.fr (Postfix) with ESMTPS id CAC8BB0040F; Wed, 4 May 2016 21:04:05 +0200 (CEST) From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 4 May 2016 23:08:39 +0200 Message-Id: <1462396135-20925-4-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1462396135-20925-1-git-send-email-laurent@vivier.eu> References: <1462392752-17703-1-git-send-email-laurent@vivier.eu> <1462396135-20925-1-git-send-email-laurent@vivier.eu> X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 212.27.42.1 Subject: [Qemu-devel] [PATCH 36/52] target-m68k: inline shift ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 211 ++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 176 insertions(+), 35 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index d183a3c..d48ab66 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -551,7 +551,7 @@ static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign) } } -static TCGv gen_extend(TCGv val, int opsize, int sign) +static inline TCGv gen_extend(TCGv val, int opsize, int sign) { TCGv tmp; @@ -2615,19 +2615,51 @@ DISAS_INSN(addx_mem) gen_store(s, opsize, addr_dest, QREG_CC_N); } -DISAS_INSN(shift_im) +static inline void shift_im(DisasContext *s, uint16_t insn, int opsize) { - TCGv reg = DREG(insn, 0); int count = (insn >> 9) & 7; int logical = insn & 8; + int left = insn & 0x100; + int bits = opsize_bytes(opsize) * 8; + TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical); + TCGv zero; - if (count == 0) { - count = 8; - } + count = ((count - 1) & 0x7) + 1; /* 1..8 */ - if (insn & 0x100) { - tcg_gen_shri_i32(QREG_CC_C, reg, 31 - count); + zero = tcg_const_i32(0); + if (left) { + tcg_gen_shri_i32(QREG_CC_C, reg, bits - count); tcg_gen_shli_i32(QREG_CC_N, reg, count); + + /* Note that ColdFire always clears V, + while M68000 sets if the most significant bit is changed at + any time during the shift operation */ + tcg_gen_mov_i32(QREG_CC_V, zero); + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + /* if shift count >= bits, V is (reg != 0) */ + if (count >= bits) { + tcg_gen_setcond_i32(TCG_COND_EQ, QREG_CC_V, reg, zero); + /* adjust V: (1,0) -> (0,-1) */ + tcg_gen_subi_i32(QREG_CC_V, QREG_CC_V, 1); + } else { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_const_i32(bits - 1 - count); + + tcg_gen_shr_i32(QREG_CC_V, reg, t1); + tcg_gen_sar_i32(t0, reg, t1); + tcg_temp_free(t1); + tcg_gen_not_i32(t0, t0); + + tcg_gen_setcond_i32(TCG_COND_EQ, QREG_CC_V, QREG_CC_V, zero); + tcg_gen_setcond_i32(TCG_COND_EQ, t0, t0, zero); + tcg_gen_or_i32(QREG_CC_V, QREG_CC_V, t0); /* V is !V here */ + + tcg_temp_free(t0); + + /* adjust V: (1,0) -> (0,-1) */ + tcg_gen_subi_i32(QREG_CC_V, QREG_CC_V, 1); + } + } } else { tcg_gen_shri_i32(QREG_CC_C, reg, count - 1); if (logical) { @@ -2635,30 +2667,28 @@ DISAS_INSN(shift_im) } else { tcg_gen_sari_i32(QREG_CC_N, reg, count); } + tcg_gen_mov_i32(QREG_CC_V, zero); } + + gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); - /* Note that ColdFire always clears V, while M68000 sets it for - a change in the sign bit. */ - if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { - tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); - } else { - tcg_gen_movi_i32(QREG_CC_V, 0); - } - - tcg_gen_mov_i32(reg, QREG_CC_N); + gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N); set_cc_op(s, CC_OP_FLAGS); } -DISAS_INSN(shift_reg) +static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize) { - TCGv reg, s32; - TCGv_i64 t64, s64; int logical = insn & 8; + int left = insn & 0x100; + int bits = opsize_bytes(opsize) * 8; + TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical); + TCGv s32; + TCGv_i64 t64, s64; + TCGv zero; - reg = DREG(insn, 0); t64 = tcg_temp_new_i64(); s64 = tcg_temp_new_i64(); s32 = tcg_temp_new(); @@ -2669,44 +2699,148 @@ DISAS_INSN(shift_reg) tcg_gen_andi_i32(s32, DREG(insn, 9), 63); tcg_gen_extu_i32_i64(s64, s32); - /* Non-arithmetic shift clears V. Use it as a source zero here. */ - tcg_gen_movi_i32(QREG_CC_V, 0); + zero = tcg_const_i32(0); - if (insn & 0x100) { - tcg_gen_extu_i32_i64(t64, reg); + tcg_gen_extu_i32_i64(t64, reg); + if (left) { + tcg_gen_shli_i64(t64, t64, 32 - bits); tcg_gen_shl_i64(t64, t64, s64); tcg_temp_free_i64(s64); tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); tcg_temp_free_i64(t64); + tcg_gen_sari_i32(QREG_CC_N, QREG_CC_N, 32 - bits); tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); + + /* Note that ColdFire always clears V, + while M68000 sets if the most significant bit is changed at + any time during the shift operation */ + tcg_gen_mov_i32(QREG_CC_V, zero); + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + + TCGv t1 = tcg_const_i32(bits - 1); + TCGv t0 = tcg_temp_new(); + + tcg_gen_sub_i32(t0, t1, s32); + tcg_gen_shr_i32(QREG_CC_V, reg, t0); + tcg_gen_sar_i32(t0, reg, t0); + tcg_gen_not_i32(t0, t0); + + tcg_gen_setcond_i32(TCG_COND_EQ, QREG_CC_V, QREG_CC_V, zero); + tcg_gen_setcond_i32(TCG_COND_EQ, t0, t0, zero); + tcg_gen_or_i32(QREG_CC_V, QREG_CC_V, t0); /* V is !V here */ + + /* if shift count >= bits, V is (reg != 0) */ + tcg_gen_setcond_i32(TCG_COND_EQ, t0, reg, zero); + tcg_gen_movcond_i32(TCG_COND_GT, QREG_CC_V, s32, t1, t0, QREG_CC_V); + + tcg_temp_free(t0); + tcg_temp_free(t1); + + /* adjust V: (1,0) -> (0,-1) */ + tcg_gen_subi_i32(QREG_CC_V, QREG_CC_V, 1); + + /* if shift count is zero, V is 0 */ + tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_V, s32, zero, + QREG_CC_V, zero); + } } else { - tcg_gen_extu_i32_i64(t64, reg); - tcg_gen_shli_i64(t64, t64, 32); + tcg_gen_shli_i64(t64, t64, 64 - bits); if (logical) { + tcg_gen_shri_i64(t64, t64, 32 - bits); tcg_gen_shr_i64(t64, t64, s64); } else { + tcg_gen_sari_i64(t64, t64, 32 - bits); tcg_gen_sar_i64(t64, t64, s64); } tcg_temp_free_i64(s64); tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64); tcg_temp_free_i64(t64); + gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31); + tcg_gen_mov_i32(QREG_CC_V, zero); } tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); - /* Note that X = C, but only if the shift count was non-zero. */ - tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, + /* C is cleared if shift count was zero */ + tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_C, s32, zero, + QREG_CC_C, zero); + + /* X = C, but only if the shift count was non-zero. */ + tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, zero, QREG_CC_C, QREG_CC_X); + tcg_temp_free(zero); tcg_temp_free(s32); - /* Note that ColdFire always clears V (which we have done above), - while M68000 sets it for a change in the sign bit. */ - if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { - tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); + /* Write back the result. */ + gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(shift8_im) +{ + shift_im(s, insn, OS_BYTE); +} + +DISAS_INSN(shift16_im) +{ + shift_im(s, insn, OS_WORD); +} + +DISAS_INSN(shift_im) +{ + shift_im(s, insn, OS_LONG); +} + +DISAS_INSN(shift8_reg) +{ + shift_reg(s, insn, OS_BYTE); +} + +DISAS_INSN(shift16_reg) +{ + shift_reg(s, insn, OS_WORD); +} + +DISAS_INSN(shift_reg) +{ + shift_reg(s, insn, OS_LONG); +} + +DISAS_INSN(shift_mem) +{ + int logical = insn & 8; + int left = insn & 0x100; + TCGv src; + TCGv addr; + + SRC_EA(env, src, OS_WORD, !logical, &addr); + tcg_gen_movi_i32(QREG_CC_V, 0); + if (left) { + tcg_gen_shri_i32(QREG_CC_C, src, 15); + tcg_gen_shli_i32(QREG_CC_N, src, 1); + + /* Note that ColdFire always clears V, + while M68000 sets if the most significant bit is changed at + any time during the shift operation */ + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + src = gen_extend(src, OS_WORD, 1); + tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); + } + } else { + tcg_gen_mov_i32(QREG_CC_C, src); + if (logical) { + tcg_gen_shri_i32(QREG_CC_N, src, 1); + } else { + tcg_gen_sari_i32(QREG_CC_N, src, 1); + } } - /* Write back the result. */ - tcg_gen_mov_i32(reg, QREG_CC_N); + gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1); + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); + + DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr); set_cc_op(s, CC_OP_FLAGS); } @@ -4451,6 +4585,13 @@ void register_m68k_insns (CPUM68KState *env) INSN(adda, d0c0, f0c0, M68000); INSN(shift_im, e080, f0f0, CF_ISA_A); INSN(shift_reg, e0a0, f0f0, CF_ISA_A); + INSN(shift8_im, e000, f0f0, M68000); + INSN(shift16_im, e040, f0f0, M68000); + INSN(shift_im, e080, f0f0, M68000); + INSN(shift8_reg, e020, f0f0, M68000); + INSN(shift16_reg, e060, f0f0, M68000); + INSN(shift_reg, e0a0, f0f0, M68000); + INSN(shift_mem, e0c0, fcc0, M68000); INSN(rotate_im, e090, f0f0, M68000); INSN(rotate8_im, e010, f0f0, M68000); INSN(rotate16_im, e050, f0f0, M68000);