From patchwork Wed May 4 22:50:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 9019401 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D569FBF29F for ; Wed, 4 May 2016 22:53:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 305A22041B for ; Wed, 4 May 2016 22:53:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 47CF5203EC for ; Wed, 4 May 2016 22:53:04 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ay5ds-0007mu-BC; Wed, 04 May 2016 22:51:40 +0000 Received: from mail-ob0-x232.google.com ([2607:f8b0:4003:c01::232]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ay5dS-0007a2-Sg for linux-arm-kernel@lists.infradead.org; Wed, 04 May 2016 22:51:15 +0000 Received: by mail-ob0-x232.google.com with SMTP id aq1so22899243obc.3 for ; Wed, 04 May 2016 15:50:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MWB0nAU7NbK6a9pA8TB2OdiSTuTH67+CYqZESuZIM48=; b=gMjGHy5uI0CshXU5q6sevVFDadu+u+UQQhUE1bw+7LPCDYzUYiJ4krp20L8y9XFST9 tTEgia4rvS4VqD1ZKW22xUgw3Csy6PXlaqhx3zA+JkdzW9XALHeCbxFUnRKZLzigX/QW 5dVOzft7C4XNG9Vv8BhKP8mbpD63Fw250C0ns= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MWB0nAU7NbK6a9pA8TB2OdiSTuTH67+CYqZESuZIM48=; b=WJdwZTqLmMcj20wSWhkbmZ0C6jHyGyAoWdrn7YFapwtg+huoVt07GcHdx0xwDpiBvV YMTz2woqBfV3jI9EYJEGljY/CApZ2Ju4VPAdhJw4hq0l6pFotNsDpZWMrmryRdyhXyre g4TZHnoW1pnsuqNhK6jOFpUAC++tFif37b2PBJVZdaQP28bXbEo48ZcSsqX+BjUJJys0 8xf65Brl/KiTfJ5OJNNlimRQFVlKAg4QGAnDprZM6FlxiWuzdpgoNzzNjhpYVfHMRxND VOgcltBiLWF7GeRc3/cJvwOaN4qRpfodH8vJMEjPh2MDodgExncOIZGyUJuq4JCRhK/N BSqg== X-Gm-Message-State: AOPr4FUXX8D5vLY7PIjuqd2hy+wqRU9mAYXVFT5bnWR7ImwlRoGVrjqgtsMZVKEeaBY5SaLi X-Received: by 10.182.233.163 with SMTP id tx3mr5437878obc.36.1462402253913; Wed, 04 May 2016 15:50:53 -0700 (PDT) Received: from localhost ([2602:306:c558:19b0:7540:9cc9:16d9:58a9]) by smtp.gmail.com with ESMTPSA id x4sm2187121obs.0.2016.05.04.15.50.53 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 04 May 2016 15:50:53 -0700 (PDT) From: Andy Gross To: linux-arm-msm@vger.kernel.org Subject: [Patch v3 3/8] firmware: qcom: scm: Use atomic SCM for cold boot Date: Wed, 4 May 2016 17:50:40 -0500 Message-Id: <1462402245-18295-4-git-send-email-andy.gross@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462402245-18295-1-git-send-email-andy.gross@linaro.org> References: <1462402245-18295-1-git-send-email-andy.gross@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160504_155114_977998_22010973 X-CRM114-Status: GOOD ( 14.02 ) X-Spam-Score: -2.7 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Stephen Boyd , linux-kernel@vger.kernel.org, Bjorn Andersson , Andy Gross , jilai wang , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch changes the cold_set_boot_addr function to use atomic SCM calls. cold_set_boot_addr required adding qcom_scm_call_atomic2 to support the two arguments going to the smc call. Using atomic removes the need for memory allocation and instead places all arguments in registers. Signed-off-by: Andy Gross --- drivers/firmware/qcom_scm-32.c | 63 ++++++++++++++++++++++++++++++------------ 1 file changed, 45 insertions(+), 18 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 0883292..5be6a12 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -342,6 +342,41 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) return r0; } +/** + * qcom_scm_call_atomic2() - Send an atomic SCM command with two arguments + * @svc_id: service identifier + * @cmd_id: command identifier + * @arg1: first argument + * @arg2: second argument + * + * This shall only be used with commands that are guaranteed to be + * uninterruptable, atomic and SMP safe. + */ +static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2) +{ + int context_id; + + register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 2); + register u32 r1 asm("r1") = (u32)&context_id; + register u32 r2 asm("r2") = arg1; + register u32 r3 asm("r3") = arg2; + + asm volatile( + __asmeq("%0", "r0") + __asmeq("%1", "r0") + __asmeq("%2", "r1") + __asmeq("%3", "r2") + __asmeq("%4", "r3") +#ifdef REQUIRES_SEC + ".arch_extension sec\n" +#endif + "smc #0 @ switch to secure world\n" + : "=r" (r0) + : "r" (r0), "r" (r1), "r" (r2), "r" (r3) + ); + return r0; +} + u32 qcom_scm_get_version(void) { int context_id; @@ -378,22 +413,6 @@ u32 qcom_scm_get_version(void) } EXPORT_SYMBOL(qcom_scm_get_version); -/* - * Set the cold/warm boot address for one of the CPU cores. - */ -static int qcom_scm_set_boot_addr(u32 addr, int flags) -{ - struct { - __le32 flags; - __le32 addr; - } cmd; - - cmd.addr = cpu_to_le32(addr); - cmd.flags = cpu_to_le32(flags); - return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, - &cmd, sizeof(cmd), NULL, 0); -} - /** * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus * @entry: Entry point function for the cpus @@ -423,7 +442,8 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) set_cpu_present(cpu, false); } - return qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + flags, virt_to_phys(entry)); } /** @@ -439,6 +459,10 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) int ret; int flags = 0; int cpu; + struct { + __le32 flags; + __le32 addr; + } cmd; /* * Reassign only if we are switching from hotplug entry point @@ -454,7 +478,10 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) if (!flags) return 0; - ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + cmd.addr = cpu_to_le32(virt_to_phys(entry)); + cmd.flags = cpu_to_le32(flags); + ret = qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + &cmd, sizeof(cmd), NULL, 0); if (!ret) { for_each_cpu(cpu, cpus) qcom_scm_wb[cpu].entry = entry;