@@ -20,7 +20,9 @@ INTEL_G4A = \
INTEL_G4I = \
exa_wm.g4i \
exa_wm_affine.g4i \
- exa_wm_projective.g4i
+ exa_wm_projective.g4i \
+ exa_wm_sample_planar.g4i \
+ exa_wm_src_sample_argb.g4i
INTEL_G4B = \
exa_sf.g4b \
@@ -61,6 +63,10 @@ INTEL_G4B_GEN5 = \
exa_wm_yuv_rgb.g4b.gen5 \
exa_wm_xy.g4b.gen5
+INTEL_G6I = \
+ exa_wm_affine.g6i \
+ exa_wm_write.g6i
+
INTEL_G6A = \
exa_wm_src_affine.g6a \
exa_wm_src_projective.g6a \
@@ -99,7 +105,8 @@ EXTRA_DIST = \
$(INTEL_G4B) \
$(INTEL_G4B_GEN5)\
$(INTEL_G6A) \
- $(INTEL_G6B)
+ $(INTEL_G6B) \
+ $(INTEL_G6I)
if HAVE_GEN4ASM
@@ -111,7 +118,7 @@ SUFFIXES = .g4a .g4b .g6a .g6b
m4 -I$(srcdir) -s $< > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m
$(INTEL_G4B): $(INTEL_G4I)
-$(INTEL_G6B): $(INTEL_G4I)
+$(INTEL_G6B): $(INTEL_G4I) $(INTEL_G6I)
BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G6B)
new file mode 100644
@@ -0,0 +1,35 @@
+/*
+ * Copyright © 2010-2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * Fragment to compute src u/v values
+ */
+
+/* U */
+pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
+pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
+
+/* V */
+pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */
+pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */
@@ -38,10 +38,4 @@ define(`bh', `g4.0<8,8,1>F')
define(`a0_a_x',`g8.0<0,1,0>F')
define(`a0_a_y',`g8.16<0,1,0>F')
-/* U */
-pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
-pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
-
-/* V */
-pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */
-pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */
+include(`exa_wm_affine.g6i')
new file mode 100644
@@ -0,0 +1,64 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang@intel.com>
+ * Keith Packard <keithp@keithp.com>
+ */
+
+/* Sample the src surface in planar format */
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* load r */
+mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable };
+
+/* src_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+
+/* sample Y */
+mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
+send (16) src_msg_ind /* msg reg index */
+ src_sample_g<1>UW /* readback */
+ null
+ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
+
+/* sample U (Cr) */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_r<1>UW /* readback */
+ null
+ sampler (3,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
+
+/* sample V (Cb) */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_b<1>UW /* readback */
+ null
+ sampler (5,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
@@ -38,10 +38,4 @@ define(`bh', `g4.0<8,8,1>F')
define(`a0_a_x',`g6.0<0,1,0>F')
define(`a0_a_y',`g6.16<0,1,0>F')
-/* U */
-pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
-pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
-
-/* V */
-pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */
-pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */
+include(`exa_wm_affine.g6i')
@@ -29,20 +29,4 @@
include(`exa_wm.g4i')
-/* prepare sampler read back gX register, which would be written back to output */
-
-/* use simd16 sampler, param 0 is u, param 1 is v. */
-/* 'payload' loading, assuming tex coord start from g4 */
-
-/* load argb */
-mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable };
-mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
-
-/* src_msg will be copied with g0, as it contains send desc */
-/* emit sampler 'send' cmd */
-send (16) src_msg_ind /* msg reg index */
- src_sample_base<1>UW /* readback */
- null
- sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
+include(`exa_wm_src_sample_argb.g4i')
new file mode 100644
@@ -0,0 +1,44 @@
+/*
+ * Copyright © 2006 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang@intel.com>
+ * Keith Packard <keithp@keithp.com>
+ */
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* load argb */
+mov (1) g0.8<1>UD 0x00000000UD { align1 mask_disable };
+mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
+
+/* src_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+send (16) src_msg_ind /* msg reg index */
+ src_sample_base<1>UW /* readback */
+ null
+ sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
+ /* here(src->dst) we should use src_sampler and src_surface */
+ mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
@@ -29,38 +29,4 @@
include(`exa_wm.g4i')
-/* prepare sampler read back gX register, which would be written back to output */
-
-/* use simd16 sampler, param 0 is u, param 1 is v. */
-/* 'payload' loading, assuming tex coord start from g4 */
-
-/* load r */
-mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable };
-
-/* src_msg will be copied with g0, as it contains send desc */
-/* emit sampler 'send' cmd */
-
-/* sample Y */
-mov (8) src_msg<1>UD g0<8,8,1>UD { align1 }; /* copy to msg start reg*/
-send (16) src_msg_ind /* msg reg index */
- src_sample_g<1>UW /* readback */
- null
- sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
-
-/* sample U (Cr) */
-send (16) src_msg_ind /* msg reg index */
- src_sample_r<1>UW /* readback */
- null
- sampler (3,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
-
-/* sample V (Cb) */
-send (16) src_msg_ind /* msg reg index */
- src_sample_b<1>UW /* readback */
- null
- sampler (5,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
- /* here(src->dst) we should use src_sampler and src_surface */
- mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */
+include(`exa_wm_sample_planar.g4i')
@@ -38,40 +38,4 @@ define(`slot_a_00', `m8')
define(`slot_a_01', `m9')
define(`data_port_msg_2_ind', `2')
-mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 };
-mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 };
-
-mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 };
-mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 };
-
-mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 };
-mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 };
-
-mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 };
-mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 };
-
-/* write */
-send (16)
- data_port_msg_2_ind
- acc0<1>UW
- null
- write (
- 0, /* binding_table */
- 16, /* pixel scordboard clear, msg type simd16 single source */
- 12, /* render target write */
- 0, /* no write commit message */
- 0 /* headerless render target write */
- )
- mlen 8
- rlen 0
- { align1 EOT };
-
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-nop;
-
+include(`exa_wm_write.g6i')
new file mode 100644
@@ -0,0 +1,61 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 };
+mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 };
+
+mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 };
+mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 };
+
+mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 };
+mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 };
+
+mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 };
+mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 };
+
+/* write */
+send (16)
+ data_port_msg_2_ind
+ acc0<1>UW
+ null
+ write (
+ 0, /* binding_table */
+ 16, /* pixel scordboard clear, msg type simd16 single source */
+ 12, /* render target write */
+ 0, /* no write commit message */
+ 0 /* headerless render target write */
+ )
+ mlen 8
+ rlen 0
+ { align1 EOT };
+
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+
It is to prepare for Xv on Ivybridge. The difference from Sandybridge is that all message payload must be in GRF registers instead of MRF registers on Ivybridge. We will only redefine some M4 macros for Ivybridge Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> --- src/render_program/Makefile.am | 13 ++++- src/render_program/exa_wm_affine.g6i | 35 ++++++++++++ src/render_program/exa_wm_mask_affine.g6a | 8 +--- src/render_program/exa_wm_sample_planar.g4i | 64 +++++++++++++++++++++++ src/render_program/exa_wm_src_affine.g6a | 8 +--- src/render_program/exa_wm_src_sample_argb.g4a | 18 +------ src/render_program/exa_wm_src_sample_argb.g4i | 44 ++++++++++++++++ src/render_program/exa_wm_src_sample_planar.g4a | 36 +------------ src/render_program/exa_wm_write.g6a | 38 +------------- src/render_program/exa_wm_write.g6i | 61 +++++++++++++++++++++ 10 files changed, 219 insertions(+), 106 deletions(-) create mode 100644 src/render_program/exa_wm_affine.g6i create mode 100644 src/render_program/exa_wm_sample_planar.g4i create mode 100644 src/render_program/exa_wm_src_sample_argb.g4i create mode 100644 src/render_program/exa_wm_write.g6i