[1/2] ARM64: dts: rockchip: add sdhci/emmc for rk3399
diff mbox

Message ID 1462924975-69072-1-git-send-email-briannorris@chromium.org
State New
Headers show

Commit Message

Brian Norris May 11, 2016, 12:02 a.m. UTC
The bindings for rk3399's SDHCI + eMMC PHY have been accepted, so let's
support eMMC now.

Note that 'rockchip,rk3399-sdhci-5.1' is not documented, but per Heiko's
previous suggestion, we don't want to clutter the arasan doc, and it's
just a precautionary measure to have it.

Signed-off-by: Brian Norris <briannorris@chromium.org>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

Comments

Shawn Lin May 11, 2016, 1:17 a.m. UTC | #1
+ Huang Lin

On 2016/5/11 8:02, Brian Norris wrote:
> The bindings for rk3399's SDHCI + eMMC PHY have been accepted, so let's
> support eMMC now.
>
> Note that 'rockchip,rk3399-sdhci-5.1' is not documented, but per Heiko's
> previous suggestion, we don't want to clutter the arasan doc, and it's
> just a precautionary measure to have it.
>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 46f325a143b0..947d1221592d 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -215,6 +215,17 @@
>  		status = "disabled";
>  	};
>
> +	sdhci: sdhci@fe330000 {
> +		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
> +		reg = <0x0 0xfe330000 0x0 0x10000>;
> +		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;

sdhci doesn't call clk_set_rate to explicitly assign clk_xin to 200MHz
as it always assumes sdhci controller should meet the highest speed of
each timing mode. And the internal divider will be used. So IMHO,
clk-rockchip for 3399 *haven't* made clk_xin to be 200MHz. Let's assign
the clk stuff to make sure it's 200MHz.

Another problem is that emmc_phy contains a configuration which should
be consistent with clk_out(namely clk_xin/internal dividor). Now I don't
submit unpstream patchset to expose these configurarion, but in
prevention of some misleading, I think it's better to to it.

How about adding these?

assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-parents = <&cru PLL_CPLL>; //may not need
assigned-clock-rates = <200000000>;

Still you limit your clk_out by adding max-frequency in dts for
specific requirment.

We here manually assigne the clk_xin to be 200MHz, so defaultly
when it's runing in HS200/HS400(ES) mode, internal divider won't
be used(by-pass mode). So the clk jitter is better when by-passing the
clock.

Thanks.

> +		clock-names = "clk_xin", "clk_ahb";
> +		phys = <&emmc_phy>;
> +		phy-names = "phy_arasan";
> +		status = "disabled";
> +	};
> +
>  	usb_host0_ehci: usb@fe380000 {
>  		compatible = "generic-ehci";
>  		reg = <0x0 0xfe380000 0x0 0x20000>;
> @@ -481,8 +492,18 @@
>  	};
>
>  	grf: syscon@ff770000 {
> -		compatible = "rockchip,rk3399-grf", "syscon";
> +		compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
>  		reg = <0x0 0xff770000 0x0 0x10000>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		emmc_phy: phy@f780 {
> +			compatible = "rockchip,rk3399-emmc-phy";
> +			reg = <0xf780 0x20>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
>  	};
>
>  	watchdog@ff840000 {
>
Brian Norris May 11, 2016, 10:31 p.m. UTC | #2
On Wed, May 11, 2016 at 09:17:38AM +0800, Shawn Lin wrote:
> + Huang Lin
> 
> On 2016/5/11 8:02, Brian Norris wrote:
> >The bindings for rk3399's SDHCI + eMMC PHY have been accepted, so let's
> >support eMMC now.
> >
> >Note that 'rockchip,rk3399-sdhci-5.1' is not documented, but per Heiko's
> >previous suggestion, we don't want to clutter the arasan doc, and it's
> >just a precautionary measure to have it.
> >
> >Signed-off-by: Brian Norris <briannorris@chromium.org>
> >---
> > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 23 ++++++++++++++++++++++-
> > 1 file changed, 22 insertions(+), 1 deletion(-)
> >
> >diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> >index 46f325a143b0..947d1221592d 100644
> >--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> >+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> >@@ -215,6 +215,17 @@
> > 		status = "disabled";
> > 	};
> >
> >+	sdhci: sdhci@fe330000 {
> >+		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
> >+		reg = <0x0 0xfe330000 0x0 0x10000>;
> >+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> >+		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
> 
> sdhci doesn't call clk_set_rate to explicitly assign clk_xin to 200MHz
> as it always assumes sdhci controller should meet the highest speed of
> each timing mode. And the internal divider will be used. So IMHO,
> clk-rockchip for 3399 *haven't* made clk_xin to be 200MHz. Let's assign
> the clk stuff to make sure it's 200MHz.
> 
> Another problem is that emmc_phy contains a configuration which should
> be consistent with clk_out(namely clk_xin/internal dividor). Now I don't
> submit unpstream patchset to expose these configurarion, but in
> prevention of some misleading, I think it's better to to it.
> 
> How about adding these?
> 
> assigned-clocks = <&cru SCLK_EMMC>;
> assigned-clock-parents = <&cru PLL_CPLL>; //may not need
> assigned-clock-rates = <200000000>;

Makes sense. Will add these.

> Still you limit your clk_out by adding max-frequency in dts for
> specific requirment.
> 
> We here manually assigne the clk_xin to be 200MHz, so defaultly
> when it's runing in HS200/HS400(ES) mode, internal divider won't
> be used(by-pass mode). So the clk jitter is better when by-passing the
> clock.
> 
> Thanks.

Brian
Brian Norris May 12, 2016, 10:22 p.m. UTC | #3
On Wed, May 11, 2016 at 09:17:38AM +0800, Shawn Lin wrote:
> How about adding these?
> 
> assigned-clocks = <&cru SCLK_EMMC>;
> assigned-clock-parents = <&cru PLL_CPLL>; //may not need

BTW, even if I assign the parent here, it's not actually taking effect
on my system. Presumably the common clock framework is finding a
"better" way to satisfy 200 MHz through GPLL instead. So I'm dropping
the assigned-clock-parents for v2.

> assigned-clock-rates = <200000000>;

Brian

Patch
diff mbox

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 46f325a143b0..947d1221592d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -215,6 +215,17 @@ 
 		status = "disabled";
 	};
 
+	sdhci: sdhci@fe330000 {
+		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
+		reg = <0x0 0xfe330000 0x0 0x10000>;
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
+		clock-names = "clk_xin", "clk_ahb";
+		phys = <&emmc_phy>;
+		phy-names = "phy_arasan";
+		status = "disabled";
+	};
+
 	usb_host0_ehci: usb@fe380000 {
 		compatible = "generic-ehci";
 		reg = <0x0 0xfe380000 0x0 0x20000>;
@@ -481,8 +492,18 @@ 
 	};
 
 	grf: syscon@ff770000 {
-		compatible = "rockchip,rk3399-grf", "syscon";
+		compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xff770000 0x0 0x10000>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		emmc_phy: phy@f780 {
+			compatible = "rockchip,rk3399-emmc-phy";
+			reg = <0xf780 0x20>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
 	};
 
 	watchdog@ff840000 {