diff mbox

[v2,10/12] tcg/tci: Add support for fence

Message ID 1464310815-13554-11-git-send-email-rth@twiddle.net (mailing list archive)
State New, archived
Headers show

Commit Message

Richard Henderson May 27, 2016, 1 a.m. UTC
Cc: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tci/tcg-target.inc.c | 3 +++
 tci.c                    | 3 +++
 2 files changed, 6 insertions(+)

Comments

Sergey Fedorov May 27, 2016, 10:23 a.m. UTC | #1
On 27/05/16 04:00, Richard Henderson wrote:
> diff --git a/tci.c b/tci.c
> index b488c0d..53b3f71 100644
> --- a/tci.c
> +++ b/tci.c
> @@ -1236,6 +1236,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
>                  tcg_abort();
>              }
>              break;
> +        case INDEX_op_fence:
> +            smp_mb();
> +            break;
>          default:
>              TODO();
>              break;

A bit of bike-shedding. While there's no common ISA term for "memory
barrier" (also known as a "membar", "memory fence", etc.), we already
refer to it as a "memory barrier" (or "mb") in include/qemu/atomic.h and
docs/atomics.txt. Why don't be consistent and avoid introducing yet
another term for the same thing?

Kind regards,
Sergey
Pranith Kumar May 27, 2016, 2:17 p.m. UTC | #2
Hi Sergey,

Sergey Fedorov writes:

> On 27/05/16 04:00, Richard Henderson wrote:
>> diff --git a/tci.c b/tci.c
>> index b488c0d..53b3f71 100644
>> --- a/tci.c
>> +++ b/tci.c
>> @@ -1236,6 +1236,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
>>                  tcg_abort();
>>              }
>>              break;
>> +        case INDEX_op_fence:
>> +            smp_mb();
>> +            break;
>>          default:
>>              TODO();
>>              break;
>
> A bit of bike-shedding. While there's no common ISA term for "memory
> barrier" (also known as a "membar", "memory fence", etc.), we already
> refer to it as a "memory barrier" (or "mb") in include/qemu/atomic.h and
> docs/atomics.txt. Why don't be consistent and avoid introducing yet
> another term for the same thing?
>

Fair point. Do you think tcg_out_mb() is better then?

Thanks,
Sergey Fedorov May 27, 2016, 2:20 p.m. UTC | #3
On 27/05/16 17:17, Pranith Kumar wrote:
> Hi Sergey,
>
> Sergey Fedorov writes:
>
>> On 27/05/16 04:00, Richard Henderson wrote:
>>> diff --git a/tci.c b/tci.c
>>> index b488c0d..53b3f71 100644
>>> --- a/tci.c
>>> +++ b/tci.c
>>> @@ -1236,6 +1236,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
>>>                  tcg_abort();
>>>              }
>>>              break;
>>> +        case INDEX_op_fence:
>>> +            smp_mb();
>>> +            break;
>>>          default:
>>>              TODO();
>>>              break;
>> A bit of bike-shedding. While there's no common ISA term for "memory
>> barrier" (also known as a "membar", "memory fence", etc.), we already
>> refer to it as a "memory barrier" (or "mb") in include/qemu/atomic.h and
>> docs/atomics.txt. Why don't be consistent and avoid introducing yet
>> another term for the same thing?
>>
> Fair point. Do you think tcg_out_mb() is better then?

Yes, if used together with 'INDEX_op_mb', of course.

Kind regards,
Sergey
Pranith Kumar May 27, 2016, 2:21 p.m. UTC | #4
On Fri, May 27, 2016 at 10:20 AM, Sergey Fedorov <serge.fdrv@gmail.com> wrote:
>>>> +        case INDEX_op_fence:
>>>> +            smp_mb();
>>>> +            break;
>>>>          default:
>>>>              TODO();
>>>>              break;
>>> A bit of bike-shedding. While there's no common ISA term for "memory
>>> barrier" (also known as a "membar", "memory fence", etc.), we already
>>> refer to it as a "memory barrier" (or "mb") in include/qemu/atomic.h and
>>> docs/atomics.txt. Why don't be consistent and avoid introducing yet
>>> another term for the same thing?
>>>
>> Fair point. Do you think tcg_out_mb() is better then?
>
> Yes, if used together with 'INDEX_op_mb', of course.
>

OK. I'll make the change. Thanks for the feedback!
diff mbox

Patch

diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c
index fa74d52..bf65416 100644
--- a/tcg/tci/tcg-target.inc.c
+++ b/tcg/tci/tcg-target.inc.c
@@ -255,6 +255,7 @@  static const TCGTargetOpDef tcg_target_op_defs[] = {
     { INDEX_op_bswap32_i32, { R, R } },
 #endif
 
+    { INDEX_op_fence, { } },
     { -1 },
 };
 
@@ -800,6 +801,8 @@  static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
         }
         tcg_out_i(s, *args++);
         break;
+    case INDEX_op_fence:
+        break;
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
diff --git a/tci.c b/tci.c
index b488c0d..53b3f71 100644
--- a/tci.c
+++ b/tci.c
@@ -1236,6 +1236,9 @@  uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
                 tcg_abort();
             }
             break;
+        case INDEX_op_fence:
+            smp_mb();
+            break;
         default:
             TODO();
             break;