| Message ID | 3573091.BUvyGW3hVt@wasted.cogentembedded.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
On Wed, Jun 01, 2016 at 01:29:05AM +0300, Sergei Shtylyov wrote: > Describe the IRQC interrupt controller in the R8A7792 device tree. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > --- > arch/arm/boot/dts/r8a7792.dtsi | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > Index: renesas/arch/arm/boot/dts/r8a7792.dtsi > =================================================================== > --- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi > +++ renesas/arch/arm/boot/dts/r8a7792.dtsi > @@ -62,6 +62,19 @@ > IRQ_TYPE_LEVEL_HIGH)>; > }; > > + irqc: interrupt-controller@e61c0000 { Could you consider using irqc0 as the node name for consistency with the DT of other R-Car Gen2 SoCs? What follows looks correct to me. > + compatible = "renesas,irqc-r8a7792", "renesas,irqc"; > + #interrupt-cells = <2>; > + interrupt-controller; > + reg = <0 0xe61c0000 0 0x200>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&mstp4_clks R8A7792_CLK_IRQC>; > + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; > + }; > + > timer { > compatible = "arm,armv7-timer"; > interrupts = <GIC_PPI 13 >
On Wed, Jun 1, 2016 at 12:29 AM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Describe the IRQC interrupt controller in the R8A7792 device tree. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On 06/01/2016 04:18 AM, Simon Horman wrote: >> Describe the IRQC interrupt controller in the R8A7792 device tree. >> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >> >> --- >> arch/arm/boot/dts/r8a7792.dtsi | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> >> Index: renesas/arch/arm/boot/dts/r8a7792.dtsi >> =================================================================== >> --- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi >> +++ renesas/arch/arm/boot/dts/r8a7792.dtsi >> @@ -62,6 +62,19 @@ >> IRQ_TYPE_LEVEL_HIGH)>; >> }; >> >> + irqc: interrupt-controller@e61c0000 { > > Could you consider using irqc0 as the node name for consistency with the > DT of other R-Car Gen2 SoCs? Frankly speaking I didn't get that name indexing thing at all. Could you share the reasoning behind it? > What follows looks correct to me. Thank you. :-) MBR, Sergei
Index: renesas/arch/arm/boot/dts/r8a7792.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi +++ renesas/arch/arm/boot/dts/r8a7792.dtsi @@ -62,6 +62,19 @@ IRQ_TYPE_LEVEL_HIGH)>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7792", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7792_CLK_IRQC>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13
Describe the IRQC interrupt controller in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/r8a7792.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)