From patchwork Wed Jun 1 08:24:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 9146345 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5D53460761 for ; Wed, 1 Jun 2016 08:24:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 316FA2040D for ; Wed, 1 Jun 2016 08:24:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 25ECE2654B; Wed, 1 Jun 2016 08:24:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9DB0C2040D for ; Wed, 1 Jun 2016 08:24:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b81Ru-0005MG-PZ; Wed, 01 Jun 2016 08:24:22 +0000 Received: from mout.kundenserver.de ([212.227.17.13]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1b81Rs-0005Au-8k for linux-rockchip@lists.infradead.org; Wed, 01 Jun 2016 08:24:21 +0000 Received: from wuerfel.localnet ([78.42.132.4]) by mrelayeu.kundenserver.de (mreue102) with ESMTPSA (Nemesis) id 0LpfUc-1bjohZ36N4-00fOJS; Wed, 01 Jun 2016 10:23:39 +0200 From: Arnd Bergmann To: Wenrui Li Subject: Re: [PATCH 2/2] pci: Add PCIe driver for Rockchip Soc Date: Wed, 01 Jun 2016 10:24:11 +0200 Message-ID: <4816755.yFEaWXVu6I@wuerfel> User-Agent: KMail/5.1.3 (Linux/4.4.0-22-generic; KDE/5.18.0; x86_64; ; ) In-Reply-To: <57482200.9090008@rock-chips.com> References: <1463740105-7061-1-git-send-email-shawn.lin@rock-chips.com> <8520D5D51A55D047800579B094147198258AF22F@XAP-PVEXMBX01.xlnx.xilinx.com> <57482200.9090008@rock-chips.com> MIME-Version: 1.0 X-Provags-ID: V03:K0:8YQhcDIG73I8nK9uEErx4OwCp9bBr77rry3M7d6u7Sx3XrfVhoK L/eSFvplwDnYtxwFSC6fm1P3or8dt0obpA2/gC9sbedUg9+Yb5gAXCp8V3zjna8hiOQIYtt W/2rc7XZUs5pfsZnLb6nWR21il9y2N+SSgj8SEapB1xmPfiLORvpernmN/f2T6/ghbSCU0x //h2kjyfzQPfKBNZXEqgA== X-UI-Out-Filterresults: notjunk:1; V01:K0:J9p7ereUF7k=:uD1h5T6BRq0pBNQPguc0Ia nTbUDsFMCBA44uE3WAtuiB7F8r2+zikLSwuD3rXmgD+rBZAjimQiaOC+RuVuUK/NcmSGq2jo7 +y3s8p+gjutfG3gL6spd6Io8NMP5z7NbvVKBHhWJ4BEm1ZAM8moeqzAjsp0Hji1uXLEPxM2NA 0NJmMOM8iSSGsq9nvwC/xhyG4dLwRnAY/xIPazHYVRPE1G8R7qtYPu/m6J5Jr8f6Q/HxpQj27 V2lB6auaY9jhS+dpbLHLtsHD+hUzTAOp/uhZOy0DjDo4j/6qEOx9/yYnrAKoeBsXSzFdKKdc7 R1WZ1XGQn9YJ0rP/XykQJUR+0/rImE3jAY87H2JgyPJGwRAJr4mbScnOAGDTXOZEO4z5DA8YT mWo3WcCxmMpEPONm1dAKEg2P1TfvHNxmERTrRE82mnsXDRQoXujIGA7VLqwzKvL87I/1oQrRm fNB+fKmK+sV9CjyEYZ8QsaW8yFkONS8Ln3U4Jq9ri5+lQ/eLuvZP34aSQhjwYkhp7Wa3bIFeP Uo5l6AP1Ng0dMIuaA9UhZLs+QAYlzY66GLaG//1rcOo0LHaZXRTiEbc7CJL9cjBO9p9TGO0VA qtDC7JeZ3LMCTa9fQ/b9Q8WNZBUytap9oySpvpphmsVoErJLH1rmyr1A10+EMiIuXYnjFK/qq Oc6hUsayHz40vue5fbB7+Nht2GBSfMuqlUS7mqJy4V0Kh6qMuEZAX0iuNHkmu+X8/CAkBpu3k vP7C9HofyEykVv59 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160601_012420_718012_43222C0D X-CRM114-Status: GOOD ( 22.99 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , Heiko Stuebner , Bharat Kumar Gogada , "linux-pci@vger.kernel.org" , Shawn Lin , Doug Anderson , "linux-kernel@vger.kernel.org" , "linux-rockchip@lists.infradead.org" , Rob Herring , Bjorn Helgaas Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On Friday, May 27, 2016 6:31:28 PM CEST Wenrui Li wrote: > Hi, > > On 2016/5/27 15:13, Bharat Kumar Gogada wrote: > >>> > >>>> + > >>>> +static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *pp, > >>>> + struct pci_bus *bus, u32 devfn, > >>>> + int where, int size, u32 *val) > >>>> +{ > >>>> + u32 busdev; > >>>> + > >>>> + busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn), > >>>> + PCI_FUNC(devfn), where); > >>>> + > >>>> + if (busdev & (size - 1)) { > >>>> + *val = 0; > >>>> + return PCIBIOS_BAD_REGISTER_NUMBER; > >>>> + } > >>>> + > >>>> + if (size == 4) { > >>>> + *val = readl(pp->reg_base + busdev); > >>>> + } else if (size == 2) { > >>>> + *val = readw(pp->reg_base + busdev); > >>>> + } else if (size == 1) { > >>>> + *val = readb(pp->reg_base + busdev); > >>>> + } else { > >>>> + *val = 0; > >>>> + return PCIBIOS_BAD_REGISTER_NUMBER; > >>>> + } > >>>> + return PCIBIOS_SUCCESSFUL; > >>>> +} > >>>> + > >>> > >>> This looks like the normal ECAM operations, you could just call those. > >> > >> I read ECAM reference code, I found it not support ioremap config space > >> for each bus individually on 64-bit systems. Our soc is 64-bit system, > >> and bus0 config space base address is 0xfda00000, bus1 base address is > >> 0xf8100000. So I think it is not normal ECAM operations, I do not know > >> if I have understood correctly? > >> > > Hi, > > > > I think Arnd was suggesting to use generic config read/write calls, pci_generic_config_read/pci_generic_config_write > > which does above functionality. > > Yeah, I seem the pci_generic_config_write use writew/writeb for byte and > word write. but our SOC not support byte and word write in RC config > spcace. So I redefine the the pci_ops.write Rihgt, that bug should be documented somewhere. You can also use the pci_generic_config_read32/pci_generic_config_write32 functions for this. I wonder if we should add a more general way of treating type 1 config space accesses differently, as a lot of host bridges have similar requirements, accessing the registers in a different place, different layout, or other constraints. The patch below would make that very easy to do. Suggestions for better naming welcome. Signed-off-by: Arnd Bergmann diff --git a/drivers/pci/access.c b/drivers/pci/access.c index d11cdbb8fba3..2f7dcaa63e1d 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -34,9 +34,12 @@ int pci_bus_read_config_##size \ u32 data = 0; \ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ raw_spin_lock_irqsave(&pci_lock, flags); \ - res = bus->ops->read(bus, devfn, pos, len, &data); \ + if (bus->number == 0 && bus->ops->read0) \ + res = bus->ops->read0(bus, devfn, pos, len, &data); \ + else \ + res = bus->ops->read(bus, devfn, pos, len, &data); \ *value = (type)data; \ - raw_spin_unlock_irqrestore(&pci_lock, flags); \ + raw_spin_unlock_irqrestore(&pci_lock, flags); \ return res; \ } @@ -48,8 +51,11 @@ int pci_bus_write_config_##size \ unsigned long flags; \ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ raw_spin_lock_irqsave(&pci_lock, flags); \ - res = bus->ops->write(bus, devfn, pos, len, value); \ - raw_spin_unlock_irqrestore(&pci_lock, flags); \ + if (bus->number == 0 && bus->ops->write0) \ + res = bus->ops->write0(bus, devfn, pos, len, value); \ + else \ + res = bus->ops->write(bus, devfn, pos, len, value); \ + raw_spin_unlock_irqrestore(&pci_lock, flags); \ return res; \ } @@ -72,7 +78,11 @@ int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, { void __iomem *addr; - addr = bus->ops->map_bus(bus, devfn, where); + if (bus->number == 0 && bus->ops->map_bus0) + addr = bus->ops->map_bus0(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where); + if (!addr) { *val = ~0; return PCIBIOS_DEVICE_NOT_FOUND; @@ -94,7 +104,10 @@ int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, { void __iomem *addr; - addr = bus->ops->map_bus(bus, devfn, where); + if (bus->number == 0 && bus->ops->map_bus0) + addr = bus->ops->map_bus0(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where); if (!addr) return PCIBIOS_DEVICE_NOT_FOUND; @@ -114,7 +127,10 @@ int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, { void __iomem *addr; - addr = bus->ops->map_bus(bus, devfn, where & ~0x3); + if (bus->number == 0 && bus->ops->map_bus0) + addr = bus->ops->map_bus0(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where & ~0x3); if (!addr) { *val = ~0; return PCIBIOS_DEVICE_NOT_FOUND; @@ -135,7 +151,10 @@ int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, void __iomem *addr; u32 mask, tmp; - addr = bus->ops->map_bus(bus, devfn, where & ~0x3); + if (bus->number == 0 && bus->ops->map_bus0) + addr = bus->ops->map_bus0(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where & ~0x3); if (!addr) return PCIBIOS_DEVICE_NOT_FOUND; diff --git a/include/linux/pci.h b/include/linux/pci.h index df41c4645911..1caae3bd7115 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -580,6 +580,9 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); + void __iomem *(*map_bus0)(struct pci_bus *bus, unsigned int devfn, int where); + int (*read0)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); + int (*write0)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); }; /*