| Message ID | 1464932075-34466-3-git-send-email-arun.siluvery@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Arun Siluvery <arun.siluvery@linux.intel.com> writes: > [ text/plain ] > Pooled EU is enabled by default for BXT but for fused down 2x6 parts it is > advised to turn it off. But there is another HW issue in these parts (fused > down 2x6 parts) before C0 that requires Pooled EU to be enabled as a > workaround. In this case the pool configuration changes depending upon > which subslice is disabled. This doesn't affect if the device has all 3 > subslices enabled. > > Userspace need to know min no. of eus in a pool as it varies based on which > subslice is disabled, this is not yet exported because userspace support is > not available yet. Once the support is available this needs to be exported > using getparam ioctls. > > Cc: Winiarski, Michal <michal.winiarski@intel.com> > Cc: Zou, Nanhai <nanhai.zou@intel.com> > Cc: Yang, Rong R <rong.r.yang@intel.com> > Cc: Tim Gore <tim.gore@intel.com> > Cc: Jeff McGee <jeff.mcgee@intel.com> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_dma.c | 10 ++++++++++ > drivers/gpu/drm/i915/i915_drv.c | 2 +- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index a6c5d87..50aedfd 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -767,6 +767,16 @@ static void gen9_sseu_info_init(struct drm_device *dev) > > if (IS_BROXTON(dev)) { > #define IS_SS_DISABLED(_ss_disable, ss) (_ss_disable & (0x1 << ss)) > + /* > + * There is a HW issue in 2x6 fused down parts that requires > + * Pooled EU to be enabled as a WA. The pool configuration > + * changes depending upon which subslice is fused down. This > + * doesn't affect if the device has all 3 subslices enabled. > + */ > + /* WaEnablePooledEuFor2x6:bxt */ > + info->has_pooled_eu = ((info->subslice_total == 3) || > + (info->subslice_total == 2 && > + INTEL_REVID(dev) < BXT_REVID_C0)); > It was agreed on irc that BXT has only one slice in all configurations. However I still think that for correctness sake, we should use info->subslice_per_slice here when we check the configuration. With that changed, Reviewed-by: Mika Kuoppala <mika.kuoppala@ıntel.com> > info->min_eu_in_pool = 0; > if (info->has_pooled_eu) { > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index de78a30..84593c1 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -357,7 +357,7 @@ static const struct intel_device_info intel_broxton_info = { > .has_ddi = 1, > .has_fpga_dbg = 1, > .has_fbc = 1, > - .has_pooled_eu = 1, > + .has_pooled_eu = 0, > GEN_DEFAULT_PIPEOFFSETS, > IVB_CURSOR_OFFSETS, > BDW_COLORS, > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index a6c5d87..50aedfd 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -767,6 +767,16 @@ static void gen9_sseu_info_init(struct drm_device *dev) if (IS_BROXTON(dev)) { #define IS_SS_DISABLED(_ss_disable, ss) (_ss_disable & (0x1 << ss)) + /* + * There is a HW issue in 2x6 fused down parts that requires + * Pooled EU to be enabled as a WA. The pool configuration + * changes depending upon which subslice is fused down. This + * doesn't affect if the device has all 3 subslices enabled. + */ + /* WaEnablePooledEuFor2x6:bxt */ + info->has_pooled_eu = ((info->subslice_total == 3) || + (info->subslice_total == 2 && + INTEL_REVID(dev) < BXT_REVID_C0)); info->min_eu_in_pool = 0; if (info->has_pooled_eu) { diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index de78a30..84593c1 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -357,7 +357,7 @@ static const struct intel_device_info intel_broxton_info = { .has_ddi = 1, .has_fpga_dbg = 1, .has_fbc = 1, - .has_pooled_eu = 1, + .has_pooled_eu = 0, GEN_DEFAULT_PIPEOFFSETS, IVB_CURSOR_OFFSETS, BDW_COLORS,
Pooled EU is enabled by default for BXT but for fused down 2x6 parts it is advised to turn it off. But there is another HW issue in these parts (fused down 2x6 parts) before C0 that requires Pooled EU to be enabled as a workaround. In this case the pool configuration changes depending upon which subslice is disabled. This doesn't affect if the device has all 3 subslices enabled. Userspace need to know min no. of eus in a pool as it varies based on which subslice is disabled, this is not yet exported because userspace support is not available yet. Once the support is available this needs to be exported using getparam ioctls. Cc: Winiarski, Michal <michal.winiarski@intel.com> Cc: Zou, Nanhai <nanhai.zou@intel.com> Cc: Yang, Rong R <rong.r.yang@intel.com> Cc: Tim Gore <tim.gore@intel.com> Cc: Jeff McGee <jeff.mcgee@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/i915_dma.c | 10 ++++++++++ drivers/gpu/drm/i915/i915_drv.c | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)