diff mbox

[1/5] drm/i915: Add support for mapping an object page by page

Message ID 1465548783-19712-1-git-send-email-ankitprasad.r.sharma@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

ankitprasad.r.sharma@intel.com June 10, 2016, 8:52 a.m. UTC 
From: Chris Wilson <chris@chris-wilson.co.uk>

Introduced a new vm specfic callback insert_page() to program a single pte in
ggtt or ppgtt. This allows us to map a single page in to the mappable aperture
space. This can be iterated over to access the whole object by using space as
meagre as page size.

v2: Added low level rpm assertions to insert_page routines (Chris)

v3: Added POSTING_READ post register write (Tvrtko)

v4: Rebase (Ankit)

v5: Removed wmb() and FLUSH_CTL from insert_page, caller to take care
of it (Chris)

v6: insert_page not working correctly without FLSH_CNTL write, added the
write again.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ankitprasad Sharma <ankitprasad.r.sharma@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/char/agp/intel-gtt.c        |  8 +++++
 drivers/gpu/drm/i915/i915_gem_gtt.c | 66 ++++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_gem_gtt.h |  5 +++
 include/drm/intel-gtt.h             |  3 ++
 4 files changed, 81 insertions(+), 1 deletion(-)

Comments

Tvrtko Ursulin June 10, 2016, 12:49 p.m. UTC | #1 
On 10/06/16 10:40, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/5] drm/i915: Add support for mapping an object page by page
> URL   : https://patchwork.freedesktop.org/series/8528/
> State : failure
>
> == Summary ==
>
> Series 8528v1 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/8528/revisions/1/mbox
>
> Test gem_exec_flush:
>          Subgroup basic-batch-kernel-default-cmd:
>                  pass       -> FAIL       (ro-byt-n2820)
> Test kms_flip:
>          Subgroup basic-flip-vs-wf_vblank:
>                  fail       -> PASS       (ro-bdw-i7-5600u)
> Test kms_pipe_crc_basic:
>          Subgroup suspend-read-crc-pipe-a:
>                  skip       -> DMESG-WARN (ro-bdw-i5-5250u)
>
> ro-bdw-i5-5250u  total:213  pass:197  dwarn:3   dfail:0   fail:0   skip:13
> ro-bdw-i7-5600u  total:213  pass:185  dwarn:0   dfail:0   fail:0   skip:28
> ro-bsw-n3050     total:213  pass:172  dwarn:0   dfail:0   fail:2   skip:39
> ro-byt-n2820     total:213  pass:173  dwarn:0   dfail:0   fail:3   skip:37
> ro-hsw-i3-4010u  total:213  pass:190  dwarn:0   dfail:0   fail:0   skip:23
> ro-hsw-i7-4770r  total:213  pass:190  dwarn:0   dfail:0   fail:0   skip:23
> ro-ilk-i7-620lm  total:213  pass:150  dwarn:0   dfail:0   fail:1   skip:62
> ro-ilk1-i5-650   total:208  pass:150  dwarn:0   dfail:0   fail:1   skip:57
> ro-ivb-i7-3770   total:213  pass:181  dwarn:0   dfail:0   fail:0   skip:32
> ro-ivb2-i7-3770  total:213  pass:185  dwarn:0   dfail:0   fail:0   skip:28
> ro-snb-i7-2620M  total:213  pass:174  dwarn:0   dfail:0   fail:1   skip:38
> fi-hsw-i7-4770k failed to connect after reboot
> ro-bdw-i7-5557U failed to connect after reboot
>
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1156/
>
> b373842 drm-intel-nightly: 2016y-06m-09d-16h-49m-09s UTC integration manifest
> 165ff1a drm/i915: Support for pread/pwrite from/to non shmem backed objects
> 7c4d2d9 drm/i915: Clearing buffer objects via CPU/GTT
> 2c60c194 drm/i915: Use insert_page for pwrite_fast
> 3f97215 drm/i915: Introduce i915_gem_object_get_dma_address()
> fbba107 drm/i915: Add support for mapping an object page by page

Copy&paste of Ankit's result analysis from another thread:

"""
Hi,

The failures seen are not introduced by the patches.
Following are the bug numbers related to the failures
https://bugs.freedesktop.org/show_bug.cgi?id=95372 -
igt/gem_exec_flush@basic-batch-kernel-default-cmd

https://bugs.freedesktop.org/show_bug.cgi?id=86365 -
igt/kms_pipe_crc_basic
"""

Chris, are you happy with merging this reduced series?

Thanks,
Ankit
Chris Wilson June 10, 2016, 12:56 p.m. UTC | #2 
On Fri, Jun 10, 2016 at 01:49:18PM +0100, Tvrtko Ursulin wrote:
> 
> On 10/06/16 10:40, Patchwork wrote:
> >== Series Details ==
> >
> >Series: series starting with [1/5] drm/i915: Add support for mapping an object page by page
> >URL   : https://patchwork.freedesktop.org/series/8528/
> >State : failure
> >
> >== Summary ==
> >
> >Series 8528v1 Series without cover letter
> >http://patchwork.freedesktop.org/api/1.0/series/8528/revisions/1/mbox
> >
> >Test gem_exec_flush:
> >         Subgroup basic-batch-kernel-default-cmd:
> >                 pass       -> FAIL       (ro-byt-n2820)
> >Test kms_flip:
> >         Subgroup basic-flip-vs-wf_vblank:
> >                 fail       -> PASS       (ro-bdw-i7-5600u)
> >Test kms_pipe_crc_basic:
> >         Subgroup suspend-read-crc-pipe-a:
> >                 skip       -> DMESG-WARN (ro-bdw-i5-5250u)
> >
> >ro-bdw-i5-5250u  total:213  pass:197  dwarn:3   dfail:0   fail:0   skip:13
> >ro-bdw-i7-5600u  total:213  pass:185  dwarn:0   dfail:0   fail:0   skip:28
> >ro-bsw-n3050     total:213  pass:172  dwarn:0   dfail:0   fail:2   skip:39
> >ro-byt-n2820     total:213  pass:173  dwarn:0   dfail:0   fail:3   skip:37
> >ro-hsw-i3-4010u  total:213  pass:190  dwarn:0   dfail:0   fail:0   skip:23
> >ro-hsw-i7-4770r  total:213  pass:190  dwarn:0   dfail:0   fail:0   skip:23
> >ro-ilk-i7-620lm  total:213  pass:150  dwarn:0   dfail:0   fail:1   skip:62
> >ro-ilk1-i5-650   total:208  pass:150  dwarn:0   dfail:0   fail:1   skip:57
> >ro-ivb-i7-3770   total:213  pass:181  dwarn:0   dfail:0   fail:0   skip:32
> >ro-ivb2-i7-3770  total:213  pass:185  dwarn:0   dfail:0   fail:0   skip:28
> >ro-snb-i7-2620M  total:213  pass:174  dwarn:0   dfail:0   fail:1   skip:38
> >fi-hsw-i7-4770k failed to connect after reboot
> >ro-bdw-i7-5557U failed to connect after reboot
> >
> >Results at /archive/results/CI_IGT_test/RO_Patchwork_1156/
> >
> >b373842 drm-intel-nightly: 2016y-06m-09d-16h-49m-09s UTC integration manifest
> >165ff1a drm/i915: Support for pread/pwrite from/to non shmem backed objects
> >7c4d2d9 drm/i915: Clearing buffer objects via CPU/GTT
> >2c60c194 drm/i915: Use insert_page for pwrite_fast
> >3f97215 drm/i915: Introduce i915_gem_object_get_dma_address()
> >fbba107 drm/i915: Add support for mapping an object page by page
> 
> Copy&paste of Ankit's result analysis from another thread:
> 
> """
> Hi,
> 
> The failures seen are not introduced by the patches.
> Following are the bug numbers related to the failures
> https://bugs.freedesktop.org/show_bug.cgi?id=95372 -
> igt/gem_exec_flush@basic-batch-kernel-default-cmd
> 
> https://bugs.freedesktop.org/show_bug.cgi?id=86365 -
> igt/kms_pipe_crc_basic
> """
> 
> Chris, are you happy with merging this reduced series?

Patch 4 (clear via CPU) is unused.

Other than that the pread/pwrite fix a hole in the API for imported
dma-buf objects, so yes they are useful.
-Chris
Tvrtko Ursulin June 13, 2016, 9:05 a.m. UTC | #3 
On 10/06/16 13:56, Chris Wilson wrote:
> On Fri, Jun 10, 2016 at 01:49:18PM +0100, Tvrtko Ursulin wrote:
>>
>> On 10/06/16 10:40, Patchwork wrote:
>>> == Series Details ==
>>>
>>> Series: series starting with [1/5] drm/i915: Add support for mapping an object page by page
>>> URL   : https://patchwork.freedesktop.org/series/8528/
>>> State : failure
>>>
>>> == Summary ==
>>>
>>> Series 8528v1 Series without cover letter
>>> http://patchwork.freedesktop.org/api/1.0/series/8528/revisions/1/mbox
>>>
>>> Test gem_exec_flush:
>>>          Subgroup basic-batch-kernel-default-cmd:
>>>                  pass       -> FAIL       (ro-byt-n2820)
>>> Test kms_flip:
>>>          Subgroup basic-flip-vs-wf_vblank:
>>>                  fail       -> PASS       (ro-bdw-i7-5600u)
>>> Test kms_pipe_crc_basic:
>>>          Subgroup suspend-read-crc-pipe-a:
>>>                  skip       -> DMESG-WARN (ro-bdw-i5-5250u)
>>>
>>> ro-bdw-i5-5250u  total:213  pass:197  dwarn:3   dfail:0   fail:0   skip:13
>>> ro-bdw-i7-5600u  total:213  pass:185  dwarn:0   dfail:0   fail:0   skip:28
>>> ro-bsw-n3050     total:213  pass:172  dwarn:0   dfail:0   fail:2   skip:39
>>> ro-byt-n2820     total:213  pass:173  dwarn:0   dfail:0   fail:3   skip:37
>>> ro-hsw-i3-4010u  total:213  pass:190  dwarn:0   dfail:0   fail:0   skip:23
>>> ro-hsw-i7-4770r  total:213  pass:190  dwarn:0   dfail:0   fail:0   skip:23
>>> ro-ilk-i7-620lm  total:213  pass:150  dwarn:0   dfail:0   fail:1   skip:62
>>> ro-ilk1-i5-650   total:208  pass:150  dwarn:0   dfail:0   fail:1   skip:57
>>> ro-ivb-i7-3770   total:213  pass:181  dwarn:0   dfail:0   fail:0   skip:32
>>> ro-ivb2-i7-3770  total:213  pass:185  dwarn:0   dfail:0   fail:0   skip:28
>>> ro-snb-i7-2620M  total:213  pass:174  dwarn:0   dfail:0   fail:1   skip:38
>>> fi-hsw-i7-4770k failed to connect after reboot
>>> ro-bdw-i7-5557U failed to connect after reboot
>>>
>>> Results at /archive/results/CI_IGT_test/RO_Patchwork_1156/
>>>
>>> b373842 drm-intel-nightly: 2016y-06m-09d-16h-49m-09s UTC integration manifest
>>> 165ff1a drm/i915: Support for pread/pwrite from/to non shmem backed objects
>>> 7c4d2d9 drm/i915: Clearing buffer objects via CPU/GTT
>>> 2c60c194 drm/i915: Use insert_page for pwrite_fast
>>> 3f97215 drm/i915: Introduce i915_gem_object_get_dma_address()
>>> fbba107 drm/i915: Add support for mapping an object page by page
>>
>> Copy&paste of Ankit's result analysis from another thread:
>>
>> """
>> Hi,
>>
>> The failures seen are not introduced by the patches.
>> Following are the bug numbers related to the failures
>> https://bugs.freedesktop.org/show_bug.cgi?id=95372 -
>> igt/gem_exec_flush@basic-batch-kernel-default-cmd
>>
>> https://bugs.freedesktop.org/show_bug.cgi?id=86365 -
>> igt/kms_pipe_crc_basic
>> """
>>
>> Chris, are you happy with merging this reduced series?
>
> Patch 4 (clear via CPU) is unused.
>
> Other than that the pread/pwrite fix a hole in the API for imported
> dma-buf objects, so yes they are useful.

I've merged patches 1-3 and 5. Thanks for the patches and review!

Regards,

Tvrtko
diff mbox

Patch

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index aef87fd..4431129 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -840,6 +840,14 @@  static bool i830_check_flags(unsigned int flags)
 	return false;
 }
 
+void intel_gtt_insert_page(dma_addr_t addr,
+			   unsigned int pg,
+			   unsigned int flags)
+{
+	intel_private.driver->write_entry(addr, pg, flags);
+}
+EXPORT_SYMBOL(intel_gtt_insert_page);
+
 void intel_gtt_insert_sg_entries(struct sg_table *st,
 				 unsigned int pg_start,
 				 unsigned int flags)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4668477..7a139a6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2355,6 +2355,28 @@  static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
 #endif
 }
 
+static void gen8_ggtt_insert_page(struct i915_address_space *vm,
+				  dma_addr_t addr,
+				  uint64_t offset,
+				  enum i915_cache_level level,
+				  u32 unused)
+{
+	struct drm_i915_private *dev_priv = to_i915(vm->dev);
+	gen8_pte_t __iomem *pte =
+		(gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+		(offset >> PAGE_SHIFT);
+	int rpm_atomic_seq;
+
+	rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
+
+	gen8_set_pte(pte, gen8_pte_encode(addr, level, true));
+
+	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+	POSTING_READ(GFX_FLSH_CNTL_GEN6);
+
+	assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
+}
+
 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 				     struct sg_table *st,
 				     uint64_t start,
@@ -2424,6 +2446,28 @@  static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
 	stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
 }
 
+static void gen6_ggtt_insert_page(struct i915_address_space *vm,
+				  dma_addr_t addr,
+				  uint64_t offset,
+				  enum i915_cache_level level,
+				  u32 flags)
+{
+	struct drm_i915_private *dev_priv = to_i915(vm->dev);
+	gen6_pte_t __iomem *pte =
+		(gen6_pte_t __iomem *)dev_priv->ggtt.gsm +
+		(offset >> PAGE_SHIFT);
+	int rpm_atomic_seq;
+
+	rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
+
+	iowrite32(vm->pte_encode(addr, level, true, flags), pte);
+
+	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+	POSTING_READ(GFX_FLSH_CNTL_GEN6);
+
+	assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
+}
+
 /*
  * Binds an object into the global gtt with the specified cache level. The object
  * will be accessible to the GPU via commands whose operands reference offsets
@@ -2543,6 +2587,24 @@  static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 	assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
 }
 
+static void i915_ggtt_insert_page(struct i915_address_space *vm,
+				  dma_addr_t addr,
+				  uint64_t offset,
+				  enum i915_cache_level cache_level,
+				  u32 unused)
+{
+	struct drm_i915_private *dev_priv = to_i915(vm->dev);
+	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
+		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
+	int rpm_atomic_seq;
+
+	rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
+
+	intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
+
+	assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
+}
+
 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
 				     struct sg_table *pages,
 				     uint64_t start,
@@ -3076,7 +3138,7 @@  static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
 	ggtt->base.bind_vma = ggtt_bind_vma;
 	ggtt->base.unbind_vma = ggtt_unbind_vma;
-
+	ggtt->base.insert_page = gen8_ggtt_insert_page;
 	ggtt->base.clear_range = nop_clear_range;
 	if (!USES_FULL_PPGTT(dev_priv))
 		ggtt->base.clear_range = gen8_ggtt_clear_range;
@@ -3116,6 +3178,7 @@  static int gen6_gmch_probe(struct i915_ggtt *ggtt)
 	ret = ggtt_probe_common(dev, ggtt->size);
 
 	ggtt->base.clear_range = gen6_ggtt_clear_range;
+	ggtt->base.insert_page = gen6_ggtt_insert_page;
 	ggtt->base.insert_entries = gen6_ggtt_insert_entries;
 	ggtt->base.bind_vma = ggtt_bind_vma;
 	ggtt->base.unbind_vma = ggtt_unbind_vma;
@@ -3147,6 +3210,7 @@  static int i915_gmch_probe(struct i915_ggtt *ggtt)
 		      &ggtt->mappable_base, &ggtt->mappable_end);
 
 	ggtt->do_idle_maps = needs_idle_maps(dev_priv->dev);
+	ggtt->base.insert_page = i915_ggtt_insert_page;
 	ggtt->base.insert_entries = i915_ggtt_insert_entries;
 	ggtt->base.clear_range = i915_ggtt_clear_range;
 	ggtt->base.bind_vma = ggtt_bind_vma;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 62be77c..163b564 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -319,6 +319,11 @@  struct i915_address_space {
 			    uint64_t start,
 			    uint64_t length,
 			    bool use_scratch);
+	void (*insert_page)(struct i915_address_space *vm,
+			    dma_addr_t addr,
+			    uint64_t offset,
+			    enum i915_cache_level cache_level,
+			    u32 flags);
 	void (*insert_entries)(struct i915_address_space *vm,
 			       struct sg_table *st,
 			       uint64_t start,
diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h
index 9e9bddaa5..f49edec 100644
--- a/include/drm/intel-gtt.h
+++ b/include/drm/intel-gtt.h
@@ -13,6 +13,9 @@  void intel_gmch_remove(void);
 bool intel_enable_gtt(void);
 
 void intel_gtt_chipset_flush(void);
+void intel_gtt_insert_page(dma_addr_t addr,
+			   unsigned int pg,
+			   unsigned int flags);
 void intel_gtt_insert_sg_entries(struct sg_table *st,
 				 unsigned int pg_start,
 				 unsigned int flags);